PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840-77
77.76MH
Z
, LVCMOS/LVTTL
O
SCILLATOR
R
EPLACEMENT
8 L
EAD
TSSOP
P
ACKAGE
O
UTLINE
- M S
UFFIX FOR
8 L
EAD
SOIC
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
T
ABLE
8A. P
ACKAGE
D
IMENSIONS
SYMBOL
N
A
A1
A2
b
c
D
E
E1
e
L
α
aaa
0.45
0°
--
4.30
0.65 BASIC
0.75
8°
0.10
--
0.05
0.80
0.19
0.09
2.90
6.40 BASIC
4.50
Millimeters
Minimum
8
1.20
0.15
1.05
0.30
0.20
3.10
Maximum
T
ABLE
8B. P
ACKAGE
D
IMENSIONS
SYMBOL
N
A
A1
B
C
D
E
e
H
h
L
α
5.80
0.25
0.40
0°
1.35
0.10
0.33
0.19
4.80
3.80
1.27 BASIC
6.20
0.50
1.27
8°
Millimeters
MINIMUM
8
1.75
0.25
0.51
0.25
5.00
4.00
MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
840AG-77
www.icst.com/products/hiperclocks.html
8
REV. A NOVEMBER 7, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
