PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83052I-01
2-B
IT
, 2:1,
S
INGLE
-E
NDED
M
ULTIPLEXER
T
ABLE
5D. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 5
Par t-to-Par t Skew; NOTE 2, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 3
Output Disable Time; NOTE 3
Test Conditions
Minimum
Typical
Maximum
250
2.7
2.9
45
TBD
Integration Range:
12KHz - 20MHz
20% to 80%
0.10
540
50
5
5
Units
MHz
ns
ns
ps
ps
ps
ps
%
ns
ns
dB
t
sk(i)
t
sk(pp)
t
jit
t
R
/ t
F
odc
t
EN
t
DIS
@100MHz
45
MUX
ISOL
MUX Isolation
NOTE 1A: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5E. AC C
HARACTERISTICS
,
V
DD
= 2.5V ± 5%, V
DDO
= 1.8V ± -0.2V, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
tp
HL
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 5
Par t-to-Par t Skew; NOTE 2, 5
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 3
Output Disable Time; NOTE 3
Test Conditions
Minimum
Typical
Maximum
250
2.9
3
43
TBD
Integration Range:
12KHz - 20MHz
20% to 80%
0.07
590
50
5
5
Units
MHz
ns
ns
ps
ps
ps
ps
%
ns
ns
dB
t
sk(i)
t
sk(pp)
t
jit
t
R
/ t
F
odc
t
EN
t
DIS
MUX
ISOL
MUX Isolation
@100MHz
45
NOTE 1A: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
www.icst.com/products/hiperclocks.html
6
83052AGI-01
REV. A NOVEMBER 24, 2004
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
