Integrated
Circuit
Systems, Inc.
ICS8302I-01
L
OW
S
KEW
, 1-
TO
-2 LVCMOS / LVTTL
F
ANOUT
B
UFFER W
/ C
OMPLEMENTARY
O
UTPUT
Test Conditions
Minimum
1.8
Typical
Maximum
250
2.7
165
800
20% to 80%
IJ 133MHz
300
45
800
55
60
Units
MHz
ns
ps
ps
ps
%
%
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
133MHz < ƒ
≤
250MHz
40
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
tp
LH
t
sk(o)
t
sk(pp)
t
R
/ t
F
odc
Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
IJ 133MHz
100
45
1.9
Test Conditions
Minimum
Typical
Maximum
250
2.9
250
900
850
55
60
Units
MHz
ns
ps
ps
ps
%
%
133MHz < ƒ
≤
250MHz
40
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AMI-01
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 2, 2005