PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843011C
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
3.3V LVPECL C
LOCK
G
ENERATOR
generating 106.25MHz output frequency. The C1 = 27pF and
C2 = 33pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 values may be slightly
adjusted for optimizing frequency accuracy.
A
PPLICATION
S
CHEMATIC
Figure 3A
shows a schematic example of the ICS843011C.
An example of LVEPCL termination is shown in this sche-
matic. Additional LVPECL termination approaches are shown
in the LVPECL Termination Application Note. In this example,
an 18 pF parallel resonant 26.5625MHz crystal is used for
VCC
R2
10
VCCA
VCC
C3
10uF
C4
0.1u
U2
Q
XTAL_OUT
1
2
3
4
VCCA
VEE
XTAL_OUT
XTAL_IN
843011C
C5
0.1u
R4
82.5
R6
82.5
VCC
Q
nQ
nc
8
7
6
5
VCC
+
Zo = 50 Ohm
R3
133
R5
133
Zo = 50 Ohm
nQ
C2
33pF
X1
26.5625MHz
18pF
-
XTAL_IN
C1
27pF
Zo = 50 Ohm
Q
+
Zo = 50 Ohm
nQ
-
R5
50
R6
50
Optional
Y-Termination
R7
50
F
IGURE
3A. ICS843011C S
CHEMATIC
E
XAMPLE
PC B
OARD
L
AYOUT
E
XAMPLE
Figure 3B
shows an example of ICS843011C P.C. board lay-
out. The crystal X1 footprint shown in this example allows
installation of either surface mount HC49S or through-hole
HC49 package. The footprints of other components in this
example are listed in the
Table 6.
There should be at least one
decoupling capacitor per power pin. The decoupling capaci-
tors should be located as close as possible to the power pins.
The layout assumes that the board has clean analog power
ground plane.
T
ABLE
6. F
OOTPRINT
T
ABLE
Reference
C1, C2
C3
C4, C5
Size
0402
0805
0603
R2
0603
NOTE: Table 6, lists component
sizes shown in this layout example.
F
IGURE
3B. ICS843011 PC B
OARD
L
AYOUT
E
XAMPLE
843011CG
www.icst.com/products/hiperclocks.html
6
REV. A JANUARY 25, 2006
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
