X24320
The next Current Address Read operation will read from
the newly loaded address.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the
Sequential Read
Sequential reads can be initiated as either a current
address read or random read. The first Data Byte is
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
transmitted as with the other modes; however, the
master now responds with an acknowledge, indicating
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
it requires additional data. The device continues to
output data for each acknowledge received. The
Address Byte 0. After the device acknowledges receipt of
the Word Address Byte 0, the master issues another
master terminates the read operation by not responding
with an acknowledge and then issuing a
stop condition.
start condition and the Slave Address Byte with the R/W bit
set to one. This is followed by an acknowledge
and then eight bits of data from the device. The master
terminates the read operation by not responding with
The data output is sequential, with the data from address n
followed by the data from address n + 1. The address
an acknowledge and then issuing a stop condition. Refer
to figure 9 for the address, acknowledge, and
data transfer sequence.
counter for read operations increments through all byte
addresses, allowing the entire memory contents to be
read during one operation. At the end of the address
space the counter “rolls over ” to address 0000h and the
The device will perform a similar operation called “Set Current
Address” if a stop is issued instead of the
device continues to output data for each acknowledge
received. Refer to figure 10 for the acknowledge and
second start shown in figure 9. The device will go into standby
mode after the stop and all bus activity will be
data transfer sequence.
ignored until a start is detected. The effect of this operation is
that the new address is loaded into the
address counter, but no data is output by the device.
Figure 9. Random Read Sequence
S
T
A
R
T
S
T
A
SIGNALS
FROM THE
MASTER
WORD ADDRESS
BYTE 1
S
T
SLAVE
ADDRESS
WORD ADDRESS
BYTE 0
SLAVE
ADDRESS
R
O
P
T
S
1
SDA BUS
S 1 0 1 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
7035 FM 11
Figure 10. Sequential Read Sequence
SIGNALS
FROM THE
MASTER
A
C
K
A
C
K
A
C
K
S
T
O
P
SLAVE
ADDRESS
SDA BUS
1
P
S
A
C
K
SIGNALS
FROM THE
SLAVE
DATA
(1)
DATA
(2)
DATA
(n–1)
DATA
(n)
(n is any integer greater than 1)
7035 FM 12
8
ICMIC [ IC MICROSYSTEMS ]
