欢迎访问ic37.com |
会员登录 免费注册
发布采购

ICM7332QG 参数 Datasheet PDF下载

ICM7332QG图片预览
型号: ICM7332QG
PDF下载: 下载PDF文件 查看货源
内容描述: 双12 /10/ 8位电压输出DAC ,串行接口和可调输出失调 [DUAL 12/10/8-BIT VOLTAGE-OUTPUT DACS with Serial Interface and Adjustable Output Offset]
分类和应用: 转换器光电二极管输出元件
文件页数/大小: 11 页 / 184 K
品牌: ICMIC [ IC MICROSYSTEMS ]
 浏览型号ICM7332QG的Datasheet PDF文件第1页浏览型号ICM7332QG的Datasheet PDF文件第2页浏览型号ICM7332QG的Datasheet PDF文件第3页浏览型号ICM7332QG的Datasheet PDF文件第5页浏览型号ICM7332QG的Datasheet PDF文件第6页浏览型号ICM7332QG的Datasheet PDF文件第7页浏览型号ICM7332QG的Datasheet PDF文件第8页浏览型号ICM7332QG的Datasheet PDF文件第9页  
ICM7372/7352/7332  
IC
mic  
DUAL 12/10/8-BIT VOLTAGE-OUTPUT DACS  
IC MICROSYSTEMS  
with Serial Interface and Adjustable Output Offset  
Symbol  
Parameter  
Test Conditions  
Min  
Typ.  
Max  
Unit  
OUTPUT CHARACTERISTICS  
Output Voltage Range  
(Note 3)  
0
VDD  
V
Short Circuit Current  
Amp Output Impedance  
Output Line Regulation  
60  
150  
mA  
VO  
SC  
At Mid-scale (Note 2)  
At 0-scale (Note 2)  
1.0  
100  
5.0  
200  
R
OUT  
0.4  
3.0  
mV/V  
V
=2.7 to 5.5 V  
DD  
LOGIC INPUTS  
Digital Input High  
(Note 2)  
(Note 2)  
2.4  
1.2  
V
V
V
IH  
IL  
Digital Input Low  
0.8  
5
V
Digital Input Leakage  
µΑ  
REFERENCE  
Reference Output  
1.25  
0.8  
1.3  
4.0  
V
V
REFOUT  
Reference Output Line  
Regulation  
mV/V  
AC ELECTRICAL CHARACTERISTICS  
(V = 2.7V to 5.5V, VOUT unloaded; all specifications T  
to T unless otherwise noted)  
MAX  
DD  
MIN  
Symbol  
SR  
Parameter  
Slew Rate  
Test Conditions  
Min  
Typ.  
Max  
Unit  
2
8
V/µs  
Settling Time  
Full-scale settling  
µs  
Mid-scale Transition Glitch  
Energy  
nV-S  
40  
Note 1: Linearity is defined from code 64 to 4095 (ICM7372)  
Linearity is defined from code 16 to 1023 (ICM7352)  
Linearity is defined from code 4 to 255 (ICM7332)  
Note 2: Guaranteed by design; not tested in production  
Note 3: See Applications Information  
Note 4: All digital Inputs at GND or VDD  
TIMING CHARACTERISTICS  
(V = 2.7V to 5.5V, all specifications T  
DD  
to T  
unless otherwise noted)  
MIN  
MAX  
Symbol  
Parameter  
SCK Cycle Time  
Test Conditions  
Min  
Typ  
Max  
Unit  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
(Note 2)  
30  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
1
2
3
4
5
6
7
Data Setup Time  
Data Hold Time  
SCK Falling edge to CS Rising Edge  
Falling Edge to SCK Rising Edge  
CS  
15  
20  
Pulse Width  
CS  
SDO Delay  
100  
Rev. A10  
ICmic reserves the right to change the specifications without prior notice.  
4