iC-TW2
8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 3/30
PACKAGES
PIN CONFIGURATION QFN24 4 mm x 4 mm
PIN FUNCTIONS
No. Name
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TP
VDD
B_V
NB_NV
A_U
NA_NU
GND
NZ_NW
Z_W
1W
VDDA
GNDA
n.c.
PINB
NINB
CLKSEL
NRST
NINA
PINA
VC
NINZ
PINZ
SCLK
CLKEXT
SDAT
+3 V to +5.5 V Digital Supply Voltage
B Signal / V Signal Output
Inverted B / Inverted V Signal Output
A Signal / U Signal Output
Inverted A / Inverted U Signal Output
Digital Ground
Inverted Z / Inverted W Signal Output
Z Signal / W Signal Output
1W-Interface, signal input
+3 V to +5.5 V Analog Supply Voltage
Analog Ground
Pin not connected
Signal Input B+
Signal Input B-
System Clock Selection Input
External Reset Input (active low)
Signal Input A-
Signal Input A+
1.2 V Reference Voltage Output
Signal Input Z- (Index)
Signal Input Z+ (Index)
2-Wire Interface, clock input
External Clock Input
2-Wire Interface, serial data in/out
Thermal Pad
(bottom side)
The
Thermal Pad
of the QFN package (bottom side) is to be connected to a ground plane on the PCB which
must have GND potential. GNDA must be wired to GND.
Only pin 1 marking on top or bottom defines the package orientation (iC-TW2 label and coding is subject
to change).