iC-NVH
6-BIT Sin/D FLASH CONVERTER
Rev D1, Page 7/13
DESCRIPTION OF FUNCTIONS
Input Amplifiers
Input stages SIN and COS are configured as instrumentation amplifiers. The gain is dependent on the amplitude
of the input signal and set via pins SG0 and SG1 according to the following table. So that the DC level to be
adjusted half of the supply voltage is available at VREF.
GAIN SELECT
Sine/Cosine Input Signal Levels Vin()
Amplitude
Average value (DC)
SG1
SG0
Gain
differential
single ended
differential
single ended
hi
hi
hi
open
lo
66.667
50.000
33.333
20.000
14.300
10.000
7.125
up to 60mVpp
up to 80mVpp
up to 120mVpp
up to 0.2Vpp
up to 0.28Vpp
up to 0.4Vpp
up to 0.56Vpp
up to 1Vpp
up to 120mVpp
up to 160mVpp
up to 240mVpp
up to 0.4Vpp
up to 0.56Vpp
up to 0.8Vpp
up to 1.1Vpp
up to 2Vpp
0.7V .. VCC-1.2V
0.7V .. VCC-1.2V
1.2V .. VCC-1.2V
1.2V .. VCC-1.2V
0.7V .. VCC-1.3V
1.2V .. VCC-1.3V
1.2V .. VCC-1.4V
1.2V .. VCC-1.6V
1.2V .. VCC-1.7V
0.7V .. VCC-1.2V
0.7V .. VCC-1.2V
1.2V .. VCC-1.3V
1.2V .. VCC-1.3V
0.8V .. VCC-1.4V
1.3V .. VCC-1.5V
1.4V .. VCC-1.7V
1.6V .. VCC-2.1V
1.8V .. VCC-2.4V
hi
open
open
open
lo
hi
open
lo
hi
lo
open
lo
4.000
lo
3.030
up to 1.3Vpp
up to 2.6Vpp
Converter Core, Transition Distance Control
For each of the 64 comparator levels the sine/cosine input signals are calculated according to the theorem of
addition and are fed into single comparators. This procedure guarantees a very high converter frequency yet also
means that consecutive comparators can switch in a very short space of time in the event of input signal
disturbances.
The comparator outputs are thus fed into a transition distance control unit. This monitors the temporal sequence
of the switching operations in such a way that each event is delayed by the length of the settable minimum gap
to the previous event. If no errors arise the transitions pass the control unit without a time delay. Synchronization
with a fixed clock pulse does not occur.
The minimum transition distance is set via an external resistor positioned between RCLK and GNDA. Alterna-
tively, pin RCLK can be shorted to VCC. Depending on the resolution maximum input frequencies of at least
200kHz are then guaranteed (see table of resolution).
Digital Processing Unit
The transition distance control unit is followed by the digital processing unit. This is where the transition events
are converted into a pulse sequence for the incremental outputs A and B. The square-wave signals generated
have a phase shift of +90° or -90°, depending on the direction of rotation. The phase relation between the
sine/cosine input signals and the A/B output signals can be set using programming pin ROT.
Alternatively, the MSB of the converter can be output to Z when ROT is high. With the zero signal this changes
to high and has the pulse length of half a cycle. This signal can be used to synchronize the high-order tracks of
an absolute-value encoder device.
ICHAUS [ IC-HAUS GMBH ]
