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IC-NQTSSOP20ET-40/125 参数 Datasheet PDF下载

IC-NQTSSOP20ET-40/125图片预览
型号: IC-NQTSSOP20ET-40/125
PDF下载: 下载PDF文件 查看货源
内容描述: 校准13位仙/ D转换器 [13-bit Sin/D CONVERTER WITH CALIBRATION]
分类和应用: 转换器
文件页数/大小: 25 页 / 1070 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-NQ  
13-bit Sin/D CONVERTER WITH CALIBRATION  
Rev D1, Page 21/25  
CFGSSI  
Code  
0x00  
Adr 0x03, Bit 7:6  
Sensor Data Output in SSI Format  
Additional bits  
E1, E0, zero bit  
none  
Ring register operation  
With SELSSI = 1 the communication timing is switched  
to SSI compatibility. Data output is in binary format  
starting with the MSB. It can be configured if the error  
bits are to be send afterwards.  
no  
0x01  
no  
0x02  
E1, E0, zero bit  
none  
yes  
yes  
0x03  
Table 38: SSI Output  
Examples of SSI formats  
SSI Output Formats  
13-bit SSI  
Res  
Mode Error CRC T1 T2 T3 T4... T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25  
10 bit SSI  
X
-
S9 S8 S7 S6 ... S0 E1 E0  
0
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop  
Example  
-
0
0
0
0
0
0
0
0
0
0
0
0
13 bit SSI  
-
S12 S11 S10 S9 ... S3 S2 S1 S0 Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop Stop  
*1  
Example  
-
0
0
0
0
0
0
0
0
0
0
0
0
SSI-R  
-
S12 S11 S10 S9 ... S3 S2 S1 S0 Stop S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2  
*2  
Example  
0
25-bit SSI  
13 bit SSI  
X
X
-
S12 S11 S10 S9 ... S3 S2 S1 S0 E1 E0  
0
0
Stop Stop Stop Stop Stop Stop Stop Stop Stop  
Example  
-
0
0
0
0
0
0
0
0
0
0
8 + 13 SSI  
bit*3  
P7 P6 P5 P4 ... P0, S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 E1 E0  
S12, S11  
Stop  
Example  
0
0
Configuration Input SLI = 0, SELSSI = 1 CFGMCD = 0x00, CFGSSI = 0x00, unless otherwise noted.  
*1 CFGSSI = 0x01; *2 CFGSSI = 0x03; *3 CFGMCD = 0x01  
Caption SSI protocol  
SSI ring operation  
Table 39: SSI Output Formats  
EEPROM INTERFACE  
Serial EEPROM components permitting operation dresses 0-111 are mapped onto the BiSS addresses  
from 3.3 V to 5 V can be connected (such as 24C02, for 16-127. If no EEPROM is connected the device must  
example). When the device is switched on the memory be configured via BiSS and address 0 written last. In  
area of bytes 0 to 15 is mapped onto iC-NQ’s registers. this case iC-NQ does not respond to addresses 16-  
The higher memory areas, bytes 16-111, are readily 119; reading addresses 120-127 sends the device ID  
available to the system via BiSS. The EEPROM ad- plus the contents of register 0 to address 124.