iC-NQL
13-bit Sin/D CONVERTER WITH SSI INTERFACE
Rev B1, Page 7/24
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
B01
B02
B03
Symbol
Parameter
Conditions
Min.
Vos()
Iin()
Vcm()
Input Offset Voltage
Input Current
Common-Mode Input Voltage
Range
V() = Vcm()
V() = 0 V ... VDDA
-20
-50
1.4
0
Typ.
Max.
20
50
VDDA-
1.5
VDDA
mV
nA
V
V
Unit
Zero Comparator
B04 Vdm()
Differential Input Voltage Range
Incremental Outputs A, B, Z
SSI Interface Output DATA
D01 Vs()hi
Saturation Voltage hi
D02 Vs()lo
D03 tr()
D04 tf()
D05 RL()
E01
E02
E03
E04
E05
E06
E07
E08
F01
F02
F03
F04
Vt()hi
Vt()lo
Vt()hys
Ipu()
fclk()
tp(CLK-
DATA)
tbusy()
tidle()
Vt()hi
Vt()lo
Vt()hys
tbusy()cfg
Saturation Voltage lo
Rise Time
Fall Time
Permissible Load at A, B
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Pull-up Current in CLK
Permissible Clock Frequency at
CLK
Vs()hi = VDD - V(); I() = -4 mA
I() = 4 mA
CL() = 50 pF
CL() = 50 pF
TMA = 1 (calibration mode)
1
0.4
0.4
60
60
V
V
ns
ns
MΩ
SSI Interface: Input CLK
2
0.8
Vt()hys = Vt()hi - Vt()lo
V() = 0 ... VDD - 1 V
300
-240
-120
-25
4
10
0
powering up with no EEPROM
1
1.5
2
0.8
Vt()hys = Vt()hi - Vt()lo
300
5
20
I() = 4 mA
V() = 0 ... VDD - 1 V
CL() = 50 pF
CLK = hi, no amplitude or frequeny error
10
60.7
1
-600
-300
7
100
0.45
-75
60
ms
V
V
mV
ms
kHz
V
µA
ns
ms
ms
MΩ
50
V
V
mV
µA
MHz
ns
Propagation Delay: CLK edge vs. all modes, RL(SLO)
≥
1 kΩ
DATA output
Processing Time
Interface Blocking Time
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Duration of Startup Configuration error free EEPROM access
Write/Read Clock at SCL
Saturation Voltage lo
Pull-up Current
Fall Time
Error Signal Indication Time at
NERR (lo signal)
EEPROM Interface, Control Logic: Inputs SDA, NERR
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR
G01 f()
G02 Vs()lo
G03 Ipu()
G04 ft()
G05 tmin()lo
G06 Tpwm()
G07 RL()
Error Signal PWM Cycle Duration fosc() subdivided by 2
22
at NERR
Permissible Load at SDA, SCL
TMA = 1 (calibration mode)