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IC-NQEVALNQ1D 参数 Datasheet PDF下载

IC-NQEVALNQ1D图片预览
型号: IC-NQEVALNQ1D
PDF下载: 下载PDF文件 查看货源
内容描述: 校准13位仙/ D转换器 [13-bit Sin/D CONVERTER WITH CALIBRATION]
分类和应用: 转换器
文件页数/大小: 25 页 / 1070 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 2/25
DESCRIPTION
iC-NQ is a monolithic A/D converter which, by ap-
plying a count-safe vector follower principle, converts
sine/cosine sensor signals with a selectable resolu-
tion and hysteresis into angle position data. This ab-
solute value is output via a high-speed synchronous-
serial BiSS interface and trails a master clock rate of
up to 10 Mbit/s, or, alternatively, can be set so that it is
compatible with SSI. A period counter supplements
the position data with a multiturn count and can be
configured for BiSS single-cycle data output.
At the same time any changes in output data are
converted into incremental A QUAD B encoder sig-
nals. Here, the minimum transition distance can be
adapted to suit the system on hand (cable length, ex-
ternal counter). A synchronised zero index is gener-
ated and output to Z if enabled by the PZERO and
NZERO inputs.
The front-end amplifiers are configured as instrumen-
tation amplifiers, permitting sensor bridges to be di-
rectly connected without the need for external resis-
tors. Various programmable D/A converters are avail-
able for the conditioning of sine/cosine sensor sig-
nals with regard to offset, amplitude ratio and phase
errors. Front-end gain can be set in stages graded
to suit all common differential sensor signals from
approximately 20 mVpp to 1.5 Vpp, and also single-
ended sensor signals from 40 mVpp to 3 Vpp respec-
tively.
Two serial interfaces have been included to per-
mit configuration of the device, connection of an
EEPROM or synchronous-serial data transfer (BiSS).
Both interfaces are bidirectional and enable the com-
plete configuration of the device including the transfer
of setup and system data to the EEPROM for perma-
nent storage. If the memory is detected following a
power-down reset, the chip setup is read in and au-
tomatically repeated if a CRC error occurs.