iC-NQC
preliminar y
Rev B1, Page 6/29
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated.
Item
No.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Total Device
Functionality and parameters beyond the operating conditions (with reference to independent voltage supplies, for instance)
are to be verified within the individual application using FMEA methods.
001
002
003
004
005
006
VDDA,
VDD
I(VDDA)
I(VDD)
Von
Vhys
Vc()hi
Permissible Supply Voltage
Supply Current in VDDA
Supply Current in VDD
Turn-on Threshold VDDA, VDD
Turn-on Threshold Hysteresis
Clamp Voltage hi at
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF
Vc()hi = V() - VDDA;
I() = 1 mA, other pins open
fin() = 200 kHz; A, B, Z open
fin() = 200 kHz; A, B, Z open
3.2
200
0.3
1.6
4.5
5.5
15
20
4.4
V
mA
mA
V
mV
V
007
Vc()lo
Clamp Voltage lo at
I() = -1 mA, other pins open
PSIN, NSIN, PCOS, NCOS,
PZERO, NZERO, VREF, NERR,
SCL, SDA, MA, SLI, SLO, A, B, Z
Clamp Voltage hi at
NERR, SCL, SDA, MA,
SLI, SLO, A, B, Z
Vc()hi = V() - VDD;
I() = 1 mA, other pins open
-1.6
-0.3
V
008
Vc()hi
0.3
1.6
V
Input Amplifiers and Signal Inputs PSIN, NSIN, PCOS, NCOS
101 Vos()
Input Offset Voltage
Vin() and G() in accordance with table GAIN;
G
≥
20
G < 20
102
103
104
105
106
107
TCos
Iin()
GA
GArel
fhc
SR
Input Offset Voltage
Temperature Drift
Input Current
Gain Accuracy
Gain SIN/COS Ratio Accuracy
Cut-off Frequency
Slew Rate
see 101
V() = 0 V ... VDDA
G() in accordance with table GAIN
G() in accordance with table GAIN
G = 80
G = 2.667
G = 80
G = 2.667
-10
-15
±10
-50
95
97
230
650
4
9
-1.0
-0.5
-10
±0.35
10
15
mV
mV
µV/K
50
102
103
nA
%
%
kHz
kHz
V/µs
V/µs
Sine-To-Digital Conversion
201
202
203
AAabs
AAabs
AArel
Absolute Angle Accuracy without referred to 360° input signal, G = 2.667,
calibration
Vin = 1.5 Vpp, HYS = 0
Absolute Angle Accuracy after
calibration
Relative Angle Accuracy
referred to 360° input signal, HYS = 0, internal
signal amplitude of 2 ... 4 Vpp
referred to signal periods at A, resp. B
(see Fig. 1);
G = 2.667, Vin = 1.5 Vpp, SELRES = 1024,
FCTR = 0x0004 ... 0x00FF, fin < fin
max
(see table 16)
I(VREF) = -1 mA ... +1 mA
1.0
+0.5
10
DEG
DEG
%
Reference Voltage Output VREF
801
VREF
Reference Voltage
48
52
%
VDDA
MHz
Oscillator
A01 fosc()max
A02
fosc()
Permissible Max. Oscillator
Frequency
Oscillator Frequency
presented at pin SCL with subdivision
of 2048;
presented at pin SCL with subdivision
of 2048;
VDDA = VDD = 5 V ±10 %, CFGOSC = 0x00
VDDA = VDD = 5 V, CFGOSC = 0x00
VDDA = VDD = 5 V, CFGOSC = 0x03
VDDA = VDD = 5 V, CFGOSC = 0x05
VDDA = VDD = 5 V
90
52
60
72
54
84
-0.1
90
83
MHz
MHz
MHz
MHz
%/K
A03
TCosc
Oscillator Frequency Tempera-
ture Drift