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IC-NQC 参数 Datasheet PDF下载

IC-NQC图片预览
型号: IC-NQC
PDF下载: 下载PDF文件 查看货源
内容描述: 与信号校准13位仙/ D转换器 [13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION]
分类和应用: 转换器
文件页数/大小: 29 页 / 1077 K
品牌: ICHAUS [ IC-HAUS GMBH ]
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iC-NQC  
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION  
Rev B1, Page 7/29  
ELECTRICAL CHARACTERISTICS  
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated.  
Item Symbol  
No.  
Parameter  
Conditions  
Unit  
Min.  
Typ.  
Max.  
A04 VCosc  
Oscillator Frequency Power Sup- CFGOSC = 0x00  
ply Dependance  
+9  
%/V  
Zero Signal Enable Inputs PZERO, NZERO  
B01 Vos()  
B02 Iin()  
Input Offset Voltage  
Input Current  
V() = Vcm()  
-20  
-50  
1.4  
20  
50  
mV  
nA  
V
V() = 0 V ... VDDA  
B03 Vcm()  
Common-Mode Input Voltage  
Range  
VDDA-  
1.5  
B04 Vdm()  
Differential Input Voltage Range  
0
VDDA  
V
Incremental Outputs A, B, Z and I/O Interface Output SLO  
D01 Vs()hi  
D02 Vs()lo  
D03 tr()  
Saturation Voltage hi  
Saturation Voltage lo  
Rise Time  
Vs()hi = VDD - V(); I() = -4 mA  
I() = 4 mA  
0.4  
0.4  
60  
V
V
CL() = 50 pF  
ns  
ns  
MΩ  
D04 tf()  
Fall Time  
CL() = 50 pF  
60  
D05 RL()  
Permissible Load at A, B  
TMA = 1 (calibration mode)  
1
I/O Interface Inputs MA, SLI  
E01 Vt()hi  
Threshold Voltage hi  
2
V
V
E02 Vt()lo  
Threshold Voltage lo  
Hysteresis  
0.8  
300  
-240  
20  
E03 Vt()hys  
E04 Ipu(MA)  
E05 Ipd(SLI)  
Vt()hys = Vt()hi - Vt()lo  
V() = 0 ... VDD - 1 V  
V() = 1 ... VDD  
mV  
µA  
µA  
Pull-up Current in MA  
Pull-down Current in SLI  
Permissible MA Clock Frequency  
-120  
120  
-25  
300  
E06  
fclk(MA)  
SSI protocol  
BiSS protocol  
4
10  
MHz  
MHz  
E07 tp(MA-  
SLO)  
Propagation Delay:  
MA edge vs. SLO output  
RL(SLO) 1 kΩ  
10  
50  
ns  
E08 tbusy_s  
Processing Time Single-Cycle  
Data (delay of start bit)  
0
µs  
E09 tbusy_r  
Processing Time Register Ac-  
cess (delay of start bit)  
with read access to EEPROM  
2
ms  
E10 tidle  
E11 t_tos  
Interface Blocking Time  
Timeout  
powering up with no EEPROM  
1
1.5  
ms  
µs  
CFGOSC = 0x00, TIMO = 0, TOA =0  
20  
EEPROM Interface Inputs SDA and Error Input NERR  
F01 Vt()hi  
F02 Vt()lo  
F03 Vt()hys  
Threshold Voltage hi  
Threshold Voltage lo  
Hysteresis  
2
V
V
0.8  
Vt()hys = Vt()hi - Vt()lo  
300  
mV  
ms  
V
F04 tbusy()cfg Duration of Startup Configuration error free EEPROM access  
F05 Vt()hi Threshold Voltage hi  
EEPROM Interface Outputs SDA, SCL and Error Output NERR  
5
7
2
G01 f()  
Write/Read Clock at SCL  
Saturation Voltage lo  
Pull-up Current  
20  
100  
0.45  
-75  
60  
kHz  
V
G02 Vs()lo  
G03 Ipu()  
G04 ft()  
I() = 4 mA  
V() = 0 ... VDD - 1 V  
CL() = 50 pF  
-600  
10  
-300  
µA  
ns  
Fall Time  
G05 tmin()lo  
Min. Duration Of Error Indication MA = hi, no BiSS access, amplitude or frequeny  
ms  
at NERR (lo signal)  
error  
G06 Tpwm()  
Cycle Duration Of Error Indica-  
tion at NERR  
fosc() subdivided 222  
60.7  
ms  
G07  
t()lo  
Duty Cycle Of Error Indication at  
NERR  
signal duration low to high;  
AERR = 0 (amplitude error)  
FERR = 0 (frequency error)  
75  
50  
%
%
G08 RL()  
Permissible Load at SDA, SCL  
TMA = 1 (calibration mode)  
1
MΩ  
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