iC-NQ
13-bit Sin/D CONVERTER WITH CALIBRATION
Rev D1, Page 7/25
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDDA = VDD = 5 V ±10 %, Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
B01
B02
B03
B04
Symbol
Parameter
Conditions
Min.
Vos()
Iin()
Vcm()
Vdm()
Input Offset Voltage
Input Current
Common-Mode Input Voltage
Range
Differential Input Voltage Range
Saturation Voltage hi
Saturation Voltage lo
Rise Time
Fall Time
Permissible Load at A, B
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Pull-up Current in MA
Pull-down Current in SLI
Permissible Clock Frequency at
MA
Vt()hys = Vt()hi - Vt()lo
V() = 0 ... VDD - 1 V
V() = 1 ... VDD
SSI protocol
BiSS B protocol: sensor mode
BiSS B protocol: register mode
10
0
0
1
0.8
300
-240
20
-120
120
-25
300
4
10
0.25
50
0
2
1.5
2
0.8
Vt()hys = Vt()hi - Vt()lo
300
5
20
I() = 4 mA
V() = 0 ... VDD - 1 V
CL() = 50 pF
MA = hi, no BiSS access, amplitude or frequeny
error
10
60.7
1
-600
-300
7
100
0.45
-75
60
ms
ms
V
V
mV
ms
kHz
V
µA
ns
ms
ms
MΩ
Vs()hi = VDD - V(); I() = -4 mA
I() = 4 mA
CL() = 50 pF
CL() = 50 pF
TMA = 1 (calibration mode)
1
2
V() = Vcm()
V() = 0 V ... VDDA
-20
-50
1.4
0
Typ.
Max.
20
50
VDDA-
1.5
VDDA
0.4
0.4
60
60
mV
nA
V
V
V
V
ns
ns
MΩ
V
V
mV
µA
µA
MHz
MHz
MHz
ns
Unit
Zero Comparator
Incremental Outputs A, B, Z and BiSS Interface Output SLO
D01 Vs()hi
D02 Vs()lo
D03 tr()
D04 tf()
D05 RL()
E01
E02
E03
E04
E05
E06
Vt()hi
Vt()lo
Vt()hys
Ipu(MA)
Ipd(SLI)
fclk(MA)
BiSS Interface: Inputs MA, SLI
E07
E08
E09
E10
F01
F02
F03
F04
tp(MA-
SLO)
tbusy()s
tbusy()r
tidle()
Vt()hi
Vt()lo
Vt()hys
tbusy()cfg
Propagation Delay: MA edge vs. all modes, RL(SLO)
≥
1 kΩ
SLO output
Processing Time Sensor Mode
Processing Time Register Mode
Interface Blocking Time
Threshold Voltage hi
Threshold Voltage lo
Hysteresis
Duration of Startup Configuration error free EEPROM access
Write/Read Clock at SCL
Saturation Voltage lo
Pull-up Current
Fall Time
Error Signal Indication Time at
NERR (lo signal)
delay of start bit
delay of start bit with read access to EEPROM
powering up with no EEPROM
EEPROM Interface, Control Logic: Inputs SDA, NERR
EEPROM Interface, Control Logic: Outputs SDA, SCL, NERR
G01 f()
G02 Vs()lo
G03 Ipu()
G04 ft()
G05 tmin()lo
G06 Tpwm()
G07 RL()
Error Signal PWM Cycle Duration fosc() subdivided 2
22
at NERR
Permissible Load at SDA, SCL
TMA = 1 (calibration mode)
ICHAUS [ IC-HAUS GMBH ]
