iC-NQC
13-bit Sin/D CONVERTER WITH SIGNAL CALIBRATION
Rev D1, Page 25/29
Bi SS
0x 00
0x 0F
0x 10
0x 1F
0x 20
RA M
0x 00
0x 0F
E EP RO M
B an k 0
B an k 0
R/W
0 x0 0 Co nf i gu r at i on
n = 0
Co nfi gu r at i on
Da ta
Da ta
0 x0 F
0 x1 0
0 x2 F
- - -
- 1 6
u nu se d
0 x3 0 n ot a vai l a b l e
0 x3 1 E DS Ba n k
0 x4 1.. .0 x7 F
0
x
3
2
P ro fi l e ID
0 x3 3
0x 3F
0 x3 4
S
e
r
i
a
l
N
u
m
b
e
r
0x 40
0x 41
0x 42
0x 43
0x 44
0x 47
0x 48
0x 77
0x 78
0x 7D
0x 7E
0x 7F
B
a
n
k
S
e
l
e
c
t
i
o
n
®
n
0 x3 7
0
x
3
8
R
R
/
W
S l ave R eg i ste r
0 x6 7
0
x
6
8
De vi ce ID
0 x6 D
0x 78
0x 7D
0x 7E
0x 7F
0
x
6
E
M
a
n
u
f
a
c
t
.
I
D
0
x
6
F
R
O
M
0 x7 0
n ot a vai l a b l e
0 x7 F
B an k 1
B
a
n
k
1
.
.
.
7
n = 1
0 x8 0
0x 00
0x 3F
0 xBF
B an k 2
0 xC0
0 xFF
R
/
W
R
n
=
2
B
a
n
k
3
n = 3
n = . .. 14
0
x
1
0
0
0
x
1
3
F
B an k 8 .. .1 5
R/W R/W
.
.
.
0
x
3
F
F
B
a
n
k
.
.
.
1
4
B
a
n
k
1
5
n
=
1
5
0 x4 00
0 x4 3F
n
o
t
a
v
a
i
l
a
b
l
e
R
P
L
0
R
P
L
1
R
e
g
i
s
t
e
r
P
r
o
t
e
c
t
i
o
n
Figure 18: Registers and addressing
STARTUP BEHAVIOR
After the supply has been turned on (power on reset), So that it is always possible to configure the setup us-
iC-NQC reads the configuration data from the EEP- ing the I/O interface - even without an EEPROM - iC-
ROM and during this phase halts error pin NERR ac- NQC first ignores parameters TIMO, TOA and RPL.
tively on a low signal (open drain output) as well as
data output SLO and the incremental signals at A, B The I/O interface can then be addressed in BiSS C
and Z on a high signal.
protocol with the longest timeout (30 µs maximum),
without safety settings being observed (cf. RPL =
Only after a successful CRC the data output to SLO 0x0).This allows the configuration to be written to RAM
and to the A, B, Z incremental outputs is released addresses 0x01 to 0x0C and to address 0x00. Ad-
and the error indication at pin NERR reset; an exter- dress 0x00 must be written to last of all and triggers an
nal pull-up resistor can supply a high signal. iC-NQC internal reset (see description on page 20).
then switches to normal operation and determines the
current angle position, providing that a sensor is con- A short timeout of 3 µs maximum can be temporar-
nected up to it and there is no amplitude error (or this ily activated by writing value 0x07 to address 0x7C
is deactivated).
(address 124d) to keep the device configuration time
shorter.
Should the CRC prove unsuccessful due to a data er-
ror (disrupted transmission, no EEPROM or the EEP- When operated without an EEPROM, iC-NQC does
ROM is not programmed), the configuration phase is not respond to higher addresses - with the exception
automatically repeated. After a third failed attempt, the of the BiSS addresses reserved for manufacturers and
procedure is aborted and error pin NERR remains ac- device IDs (0x78 to 0x7F). This address area supplies
tive, displaying a permanent low.
the chip version from the ROM.
After startup, iC-NQC does not recognize a defined
configuration; the configuration RAM can contain any
values.
ICHAUS [ IC-HAUS GMBH ]
