iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 7/39
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 °C...125 °C, IBN calibrated to 200 µA, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
0.8
118 ∆PHI12
Phase Error Calibration Step
Width
0.63
°
°
119 INL(PHI12) Integral Linearity Error of Phase limited test coverage (guaranteed by design)
Calibration
-0.8
120 fin()
Permissible Maximum Input Freq. analog signal path
Output Voltage at X2 BIASEX = 10, I(X2) = 0, referenced to VRE-
Fin12
200
95
kHz
%
121 Vout(X2)
100
105
122 Vin(X2)
123 Rin(X2)
Permissible Input Voltage Range BIASEX = 11
at X2
0.5
20
VDDS
− 2
30
V
Input Resistance at X2
BIASEX = 11, RIN0(3:0) = 0x01, RIN12(3:0) =
27
kΩ
0x01
Sine-To-Digital Conversion
201 AAabs Absolute Angle Accuracy
referenced to 360° input signal, ideal waveform,
quasi static signals, adjusted signal condition-
ing, SELHYS = 0
0.9
1.8
°
202
AArel
Relative Angle Accuracy
referenced to output period T (see Fig. 1), ideal
waveform, quasi static signals;
at 4 edges per period
10
10
10
10
%
%
%
%
at 100 edges per period
at 384 edges per period
at 400 edges per period
<0.5
<2
203 AAR
Repeatability
see 201; VDD = const., Tj = const.
0.1
°
Line Driver Outputs PA, NA, PB, NB, PZ, NZ
501
Vs()hi
Saturation Voltage hi
Vs() = VDD - V();
SIK(1:0) = 00, I() = -1.2 mA
SIK(1:0) = 01, I() = -4 mA
SIK(1:0) = 10, I() = -20 mA
SIK(1:0) = 11, I() = -50 mA
200
200
400
700
mV
mV
mV
mV
502
503
Vs()lo
Isc()hi
Saturation Voltage lo
SIK(1:0) = 00, I() = 1.2 mA
SIK(1:0) = 01, I() = 4 mA
SIK(1:0) = 10, I() = 20 mA
SIK(1:0) = 11, I() = 50 mA
200
200
400
700
mV
mV
mV
mV
Short-Circuit Current hi
V() = 0 V;
SIK(1:0) = 00
SIK(1:0) = 01
SIK(1:0) = 10
SIK(1:0) = 11
-4
-12
-60
-150
-1.2
-4
-20
-50
mA
mA
mA
mA
504
505
506
Isc()lo
tr()
Short-Circuit Current lo
Rise Time
V() = VDD;
SIK(1:0) = 00
SIK(1:0) = 01
SIK(1:0) = 10
SIK(1:0) = 11
1.2
4
20
50
4
12
60
150
mA
mA
mA
mA
RL = 100 Ω to GND;
SSR(1:0) = 00
SSR(1:0) = 01
SSR(1:0) = 10
SSR(1:0) = 11
5
5
20
50
20
40
140
350
ns
ns
ns
ns
tf()
Fall Time
RL = 100 Ω to VDD;
SSR(1:0) = 00
SSR(1:0) = 01
SSR(1:0) = 10
SSR(1:0) = 11
5
5
30
50
20
40
140
350
ns
ns
ns
ns
507 Ilk()tri
508 IIk()rev
509 Rin()cal
510 I()cal
Leakage Current
TRIHL(1:0) = 11 (tristate)
reversed supply voltage
20
100
2.5
100
µA
µA
kΩ
µA
Leakage Current
Test Signal Source Impedance
Permissible Test Signal Load
Op. modes Calibration 1, 2, 3
Op. modes Calibration 1, 2, 3
4
3
-3
511
tclk()lo
Clock Signal Low-Pulse Duration
for CP, CPD, CPU
Op. mode Mode 191/193;
MTD = 0x0
110
800
ns
ns
MTD = 0x7
512 tw()hi
Duty Cycle
referenced to output period T, see Fig. 1
50
%
ICHAUS [ IC-HAUS GMBH ]
