iC-MP
8-BIT HALL ANGLE ENCODER
WITH RATIOMETRIC OUTPUT
Rev B1, Page 7/22
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 5 V ±10 % , Tj = -40 ... 125 °C, unless otherwise stated
Item
No.
503
504
505
506
507
508
601
602
603
604
605
606
607
701
702
703
704
705
706
801
802
803
902
904
905
906
907
908
909
910
911
912
913
Symbol
Vt1()hys
Vt2()hi
Vt2()lo
Vt2()hys
Vzap()
Izap()
Vt()hi
Vt()lo
Vt()hys
Ipu()
fclk(MA)
tzap(MA)
tout(MA)
Vs()hi
Vs()lo
Isc()hi
Isc()lo
tr()
tf()
Vs()lo
Ilk()
Isc()lo
VREF
Parameter
Threshold Hysteresis
Voltage Threshold hi vs. VDD
Voltage Threshold lo vs. VDD
Threshold Hysteresis
Permissible Zapping Voltage
Required Zapping Current
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
Input Pull-up Current
Permissible Clock Frequency at
MA
Vt()hys = Vt()hi
−
Vt()lo
V() = 0...VDD
−
1 V
Normal mode
0.8
230
-240
0.080
4.5
5
-120
-10
10
5.5
15
0.4
0.4
-90
10
-10
90
60
60
0.4
-5
4.5
45
50
2
VREF
2
VREF
2
VREF
2
VREF
-50
0.95
50
1.05
5
90
55
Conditions
Min.
Vt1()hys = Vt1()hi
−
Vt1()lo
Vt2()hi = V() - VDD,
VDD = 5 V ±5%, Tj = 10 ... 40 °C
Vt2()lo = V() - VDD;
VDD = 5 V ±5%, Tj = 10 ... 40 °C
Vt2()hys = Vt2()hi
−
Vt2()lo
VDD = 5 V ±5%, Tj = 10 ... 40 °C
VDD = 5 V ±5%, Tj = 10 ... 40 °C
0.7
20
7.3
7.4
150
7.5
90
2
230
Typ.
Max.
400
1.3
mV
V
V
mV
V
mA
V
V
mV
µA
MHz
µs
µs
V
V
mA
mA
ns
ns
V
µA
mA
%VDD
Vpp
V
Vpp
V
Vpp
V
Vpp
V
mV
Unit
Serial Interface and Power Save Mode Inputs: MA, SLI, PSMI
Permissible Zapping Cycle at MA Programming mode,
VDD = 5 V ±5%, Tj = 10 ... 40 °C
Interface Timeout
Saturation Voltage hi
Saturation Voltage lo
Short-Circuit Current hi
Short-Circuit Current lo
Rise Time
Fall Time
Saturation Voltage lo
Leakage Current
Short-Circuit Current lo
Reference Voltage at LAO
Time from MA last edge to SLO lo
→
hi
Vs()hi = VDD
−
V(), I() = -4 mA
I() = 4 mA
V() = 0 V
V() = VDD
CL() = 50 pF, V(): 20
→
80%
CL() = 50 pF, V(): 80
→
20%
I() = 4 mA
V() = 0...VDD, PSMI = hi
V() = VDD
Op. mode: Test 2
Op. mode: Test 0
Op. mode: Test 0
Op. mode: Test 0
Op. mode: Test 0
Op. mode: Test 1
Op. mode: Test 1
Op. mode: Test 1
Op. mode: Test 1
dVoff() = V(PSIN)
−
V(NSIN),
dVoff() = V(PCOS)
−
V(NCOS)
VR() = V(PSIN) / V(PCOS),
VR() = V(NSIN) / V(NCOS)
Serial Interface and Power Save Mode Outputs: SLO, PSMO
I/O Interface NERR
Test Signals at NERR, LAO, PSMO (iC-Haus device test only)
Vpp(PSIN) Pos. Sine Sensor AC Signal
at NERR
Vdc(PSIN) Pos. Sine Sensor DC Signal
at NERR
Vpp(PCOS) Pos. Cosine Sensor AC Signal
at LAO
Vdc(PCOS) Pos. Cosine Sensor DC Signal
at LAO
Vpp(NSIN) Neg. Sine Sensor AC Signal
at NERR
Vdc(NSIN) Neg. Sine Sensor DC Signal
at NERR
Vpp(NCOS) Neg. Cosine Sensor AC Signal
at LAO
Vdc(NCOS) Neg. Cosine Sensor DC Signal
at LAO
dVoff()
VR()
Diff. Sine and Cosine Signal
Offsets
Sine/Cosine AC Signal Ratio
ICHAUS [ IC-HAUS GMBH ]
