iC-MN 25-BIT NONIUS ENCODER
WITH 3-CH. SAMPLING 13-BIT Sin/D INTERPOLATION
Rev D1, Page 30/59
S/D CONVERSION with NONIUS CALCULATION
For the nonius modes iC-MN has a flash counter which Output Data Verification
counts the zero crossings of the master track. When It is possible to verify the counted period when a non-
the system is started this flash counter is preloaded ius calculation has been completed. Possible settings
with the absolute period information which has been include:
most recently calculated using the nonius and segment
tracks (or only the nonius track).
1. No verification of counted periods
The output data word always is the flash counter value
2. Frequency-dependent verification of counted pe-
synchronized with the master track. Furthermore, it is
riods. Exceeding the maximum master track sig-
possible to output synchronized singleturn and multi-
nal frequency set by FRQ_TH (see Table 46) dis-
turn position data which can be set using the parame-
ables the flash counter verification versus nonius
ter MODE_MT (see page 46).
calculation. If the limit is again undershot, future
conversions are again verified.
MODE_ST
Addr. 0x3D; bit 7:4
Operation modes with nonius calculation (Nonius Modes)
3. Period verification versus nonius calculation is al-
ways enabled and executed with each conver-
sion.
Code
Description
Data outp. following S/D conversion of master track
Period verification disabled
0x00
0x01
0x02
Frequency-dependent period verification
Period verification enabled
Op. Mode Descriptions Of Nonius Modes
Data output following S/D conversion of all tracks
Frequency-dependent period verification
Period verification enabled
0x03
0x04
MODE_ST Codes 0x00, 0x01, 0x02
With this mode the processing time is largely deter-
mined by the conversion time of the master track. The
conversion procedure is as follows:
Zero-delay data output: result of previously
triggered S/D conversion
0x05
0x06
0x07
Period verification disabled
Frequency-dependent period verification
Period verification enabled
1. A data readout request triggers the conversion of
all selected tracks
Zero-delay data output: last result of background
S/D conversion (asynchronous)
0x08
0x09
0x0A
Period verification disabled
2. Following conversion of the master track: syn-
chronization with the internal flash counter and
output of the synchronized postion value
Frequency-dependent period verification
Period verification enabled
Zero-delay data output: last result of S/D
conversion triggered by pin T3
3. During data readout: conversion of the remaining
tracks and nonius calculation
0x0B
Period verification enabled
Notes
On changing parameter MODE_ST during
operation command SOFT_RES should be issued.
4. Generation of NON_CTR with the next data read-
out cycle
Modes 0x08, 0x09, 0x0A are not permitted during
calibration via Op.Mode’s ANA_x oder DIGx_x.
Table 42: Nonius modes
MODE_ST Codes 0x03, 0x04
The processing time is largely determined by the sum
of the conversion time of the tracks for conversion. The
conversion procedure is as follows:
1. A data readout triggers the complete conversion
of the set tracks
2. Following conversion of the master track: syn-
chronization with the internal flash counter
3. Following conversion of the remaining tracks: no-
nius calculation and generation of NON_CTR
ICHAUS [ IC-HAUS GMBH ]
