iC-MB4
BiSS INTERFACE MASTER
Rev B2, Page 11/40
OPERATING REQUIREMENTS: µC Interface, INTEL mode
Operating conditions: CFGSPI = 0, INT_NMOT = 1, VDD = 3.0 . . . 5.5 V, Tj = -40 . . . 125 °C
lo input level = 0 . . . 0.8 V, hi input level = 2.0 V . . . VDD, lo output level = 0 . . . 0.4 V, hi output level = 2.4 V . . . VDD
Alias: NRD = NRD_RNW, NWR = NWR_E
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Max.
I001 tsCA
I002 tsDA
I003 thDA
I004 tAh
Setup Time:
NCS lo before ALE hi→lo
Setup Time:
Data stable before ALE hi→lo
Hold Time:
Data stable after ALE hi→lo
Signal Duration:
ALE at high level
10
15
15
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
I005 tsAR
I006 thAR
I007 tRl
Setup Time:
ALE lo before NRD hi→lo
Hold Time:
ALE lo after NRD lo→hi
Signal Duration:
NRD at low level
NCS = lo
NCS = lo
I008 tpRD1
I009 tpRD2
Propagation Delay:
Data stable after NRD hi→lo
Propagation Delay:
Data bus high impedance after NRD
lo→hi
Hold Time:
NCS lo after NRD lo→hi
Setup Time:
ALE lo before NWR hi→lo
Hold Time:
ALE lo after NWR lo→hi
Signal Duration:
NWR at low level
NCS = lo, CL = 50 pF
NCS = lo, CL = 50 pF
25
25
I010 thCR
I011 tsAW
I012 thAW
I013 tWl
10
10
10
10
15
15
10
ns
ns
ns
ns
ns
ns
ns
NCS = lo
NCS = lo
NCS = lo
NCS = lo
I014 tsDW
I015 thDW
I016 thCW
Setup Time:
Data stable before NWR lo→hi
Hold Time:
Data stable after NWR lo→hi
Hold Time:
NCS lo after NWR lo→hi
Figure 3: Read cycle (Intel mode)
Figure 4: Write cycle (Intel mode)
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