iC-LV
5ꢀBITꢁOPTOꢁENCODER
RevꢁA3,ꢁPageꢁ10/12
Analog Test Modes (MODE = 0)
Theꢁ synchronizationꢁ resultꢁ isꢁ switchedꢁ straight
throughꢁtoꢁtheꢁoutputꢁsoꢁthatꢁaꢁsynchronizedꢁMSBꢁis
availableꢁ forꢁ eachꢁ followingꢁ gear.ꢁ Thisꢁ allowsꢁ the
trackꢁdataꢁtoꢁbeꢁsynchronizedꢁwithꢁMSBsꢁonꢁtheꢁfirst
fallingꢁasꢁwellꢁasꢁonꢁtheꢁfirstꢁrisingꢁedge.
Sensor emulation and comparator switching
threshold test:ꢁ Toꢁ testꢁ theꢁ trackꢁ evaluationꢁ and
switchingꢁthresholdsꢁaꢁtestꢁcurrentꢁisꢁsuppliedꢁatꢁpin
SYNM0ꢁforꢁreferenceꢁsensorꢁDREFꢁandꢁatꢁSYNM1ꢁfor
theꢁ trackꢁ sensors.ꢁ Theꢁ currentꢁ reductionꢁ ratioꢁ is
1:1000.
InꢁsynchronizationꢁmodesꢁiCꢀLVꢁfunctionsꢁasꢁaꢁ4ꢀbit
shiftꢁ register,ꢁ i.e.ꢁ theꢁ synchronizationꢁ bitꢁ isꢁ not
clockedꢁoutꢁwithꢁtheꢁtrackꢁdata.ꢁSerialꢁdataꢁisꢁreadꢁin
onꢁaꢁfallingꢁedgeꢁandꢁoutputꢁonꢁaꢁrisingꢁedge.ꢁInꢁSSI
OutꢁmodeꢁtheꢁMSBꢁisꢁblankedꢁoutꢁbyꢁaꢁhighꢁuntilꢁthe
firstꢁ risingꢁ edgeꢁ andꢁ thusꢁ outputꢁ onꢁ thisꢁ firstꢁ rising
edge,ꢁmakingꢁthisꢁmodeꢁSSIꢁcompatible.
Alternatively,ꢁtestingꢁcanꢁbeꢁcarriedꢁoutꢁbyꢁillumination
asꢁ theꢁ suppliedꢁ testꢁ currentsꢁ areꢁ addedꢁ toꢁ the
photocurrents.ꢁTheꢁtrackꢁtoꢁbeꢁmeasuredꢁatꢁSOUTꢁis
selectedꢁviaꢁaꢁ5ꢀbitꢁshiftꢁregister.ꢁToꢁthisꢁendꢁaꢁsuitꢀ
ableꢁbitꢁstreamꢁisꢁclockedꢁinꢁviaꢁSCLKꢁ(clockꢁlowꢁacꢀ
tive)ꢁandꢁSERINꢁ(level).ꢁIfꢁmoreꢁthanꢁoneꢁtrackꢁisꢁseꢀ
lected,ꢁtheꢁcomparatorꢁoutputꢁsignalsꢁareꢁEXORed.
Theꢁ5ꢀbitꢁshiftꢁregisterꢁaddressesꢁtrackꢁsensorsꢁD4ꢁto
D0ꢁviaꢁbitsꢁ4ꢁtoꢁ0.ꢁWhenꢁmeasurementꢁcommences
theꢁshiftꢁregisterꢁshouldꢁbeꢁfilledꢁupꢁwithꢁzero.
MSB
LSB
D4D3D2D1D0
DB(0)
binaryꢁLSB
GRAY2BIN
4
&
1
IDDQ test:ꢁ Thisꢁ testꢁ isꢁ initiatedꢁ byꢁ connectingꢁ pin
NDIRꢁ(defaultꢁhigh)ꢁtoꢁGND.
SERIN
binaryꢁMSBꢁof
predecessor
&
ADDꢁ/SUB
SEEN
Digital Test Modes (MODE = 1, open)
SOUT
Logic test:ꢁDigitalꢁtestꢁmodeꢁisꢁlargelyꢁidenticalꢁtoꢁthe
serialꢁoperatingꢁmodes.ꢁOneꢁdifferenceꢁisꢁthatꢁdata
inputꢁatꢁpinꢁSERINꢁisꢁfirstꢁclockedꢁthroughꢁaꢁ5ꢀbitꢁshift
registerꢁbeforeꢁbeingꢁclockedꢁthroughꢁtheꢁoutputꢁshift
register.ꢁ Thisꢁ enablesꢁ variousꢁ bitꢁ sequencesꢁ toꢁ be
firstꢁclockedꢁintoꢁtheꢁtestꢁregister.ꢁFollowingꢁanꢁidle
timeꢁonꢁtheꢁclockꢁlineꢁofꢁtꢁ>ꢁtmfꢁ(seeꢁElectricalꢁCharꢀ
acteristicsꢁNo.ꢁ603)ꢁtheꢁtestꢁdataꢁisꢁstoredꢁonꢁtheꢁfirst
fallingꢁedgeꢁonꢁSCLKꢁinsteadꢁofꢁtheꢁtrackꢁvalues.
SERINꢁmountedꢁleadingꢁSEENꢁ=ꢁ'1'ꢁ
ifꢁDBꢁ='1'ꢁandꢁSERINꢁ='0'
DB(4:1)ꢁ+ꢁ1
DB(4:1)ꢁꢀꢁ1
SERINꢁmountedꢁtrailingꢁSEENꢁ=ꢁ'0'ꢁ
ifꢁDBꢁ='0'ꢁandꢁSERINꢁ='1'
Figureꢁ2:ꢁSynchronization
IfꢁinvertedꢁGrayꢁcodesꢁareꢁusedꢁonꢁtheꢁcodeꢁdiscsꢁa
codeꢁinversionꢁcanꢁbeꢁinitiatedꢁbyꢁconnectingꢁNINVꢁto
GND.ꢁByꢁconnectingꢁ NDIRꢁtoꢁGNDꢁtheꢁMSBꢁbitꢁis
outputꢁinvertedꢁtoꢁreverseꢁtheꢁcountꢁdirectionꢁofꢁthe
Grayꢁcode.
HereꢁitꢁshouldꢁbeꢁnotedꢁthatꢁinvertingꢁtheꢁMSBꢁoutput
causesꢁaꢁ180°ꢁchangeꢁinꢁtheꢁphaseꢁposition,ꢁi.e.ꢁa
trailingꢁ90°ꢁsynchronizationꢁtrackꢁbecomesꢁaꢁleading
90°ꢁtrackꢁandꢁviceꢁversa.ꢁThisꢁcanꢁbeꢁcompensated
forꢁbyꢁaꢁsuitableꢁsettingꢁofꢁpinꢁSEENꢁorꢁbyꢁassembling
theꢁcodeꢁdiscꢁinꢁaꢁsuitableꢁzeroꢁposition.
Thisꢁallowsꢁvariousꢁsensorꢁinputꢁstimuliꢁtoꢁbeꢁgenerꢀ
ated.ꢁInꢁtheꢁsynchronizedꢁoperatingꢁmodesꢁtheꢁdata
wordꢁisꢁsynchronizedꢁwithꢁpinꢁSERINꢁasꢁinꢁnormal
operatingꢁmode.ꢁConfigurationꢁofꢁtheꢁvariousꢁserial
operatingꢁmodesꢁisꢁalsoꢁasꢁinꢁnormalꢁoperatingꢁmode.
Noꢁ stimuliꢁ canꢁ beꢁ clockedꢁ inꢁ inꢁ No Sync Binary
mode.
TP:ꢁSoꢁthatꢁtheꢁswitchingꢁthresholdsꢁofꢁtheꢁinputꢁinterꢀ
facesꢁ(SYNM0,ꢁSYNM1,ꢁSERIN,ꢁSCLK,ꢁNDIR,ꢁNINV,
SEEN)ꢁ canꢁ beꢁ measuredꢁ theꢁ signalsꢁ areꢁ EXORed
andꢁoutputꢁatꢁpinꢁNERR.ꢁToꢁthisꢁendꢁpinꢁNERRꢁis
switchedꢁasꢁaꢁpushꢀpullꢁoutput.
Test modes
iCꢀLVꢁhasꢁtwoꢁdifferentꢁtestꢁmodesꢁwhichꢁareꢁactiꢀ
vatedꢁbyꢁconnectingꢁpinꢁTESTꢁtoꢁVDD.ꢁPinꢁMODE
designatesꢁwhichꢁtestꢁmodeꢁisꢁactivated.ꢁConnected
toꢁVDDꢁ(orꢁnotꢁconnectedꢁatꢁall),ꢁthisꢁinitiatesꢁtheꢁdigiꢀ
talꢁtestꢁmode;ꢁifꢁconnectedꢁtoꢁGNDꢁtheꢁanalogꢁtest
modeꢁisꢁselected.
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