iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 30/35
INCREMENTAL OUTPUT
Selecting the output
A valid Z pulse is only output at pin INCZ when Flex-
At pins INCA and INCB incremental signals are output Count is enabled (INC = 0x07).
with either various interpolation factors or FlexCount
resolutions. Selection is made using parameter INC.
Output in digital test and iC-Haus test modes is de-
scribed in the section on test functions on page 33.
INC
Addr. 0x08; bit 6:4
Function
Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
Tristate
The incremental signal pins (INCA/INCB/INCZ) can be
switched to tristate using register bit TRIABZ. After a
power-on TRIABZ is initialized with a 1.
Interpolation factor x1
Interpolation factor x2
Interpolation factor x4
Interpolation factor x8
Interpolation factor x16
iC-Haus digital test
iC-Haus test
TRIABZ
Addr. 0x0B; bit 3
Code
Pin function of INCA, INCB, INCZ
Push-pull (incremental signals)
Tristate
0
1
FlexCount
Table 42: Incremental output options
Table 43: Incremental output tristate
SHIFT REGISTER OUTPUT
NSL
Latch
CLK
MSB
MSB-1
LSB
DIN
DOUT
NSL
Latch
CLK
MSB
MSB-1
LSB
DIN
DOUT
Figure 20: Shift register output
iC-LNB has a shift register for position data readout. In can occur during data transmission and is not time crit-
order to enable this shift register the sensor data chan- ical.
nel for the SPI interface must be disabled by command
ACTIVATE (table 12). After power-on the shift register
in iC-LNB is active and the sensor data channel of the
SPI interface is deactivated.
RNF is used to select an output level at pin DOUT for
idle state - either idle 1 (high) or the MSB bit in real
time. External data can be read into iC-LNB through
shift register input pin DIN. This is output after the posi-
tion data. The position data readout process is shown
in Figure 20.
The position data is output in Gray code or binary code
(depending on parameter NGRAY), with the MSB first.
If pin NSL = 1, the position data is loaded into the shift
register on the first falling edge at pin CLK. Following
this, the data is clocked out on each rising edge at pin
CLK, regardless of the level at pin NSL.
The shift register returns to its idle state on a rising The length of the shift register and the number of data
edge at NSL. This means that the falling edge at NSL bits used can be selected using parameter SRC.
ICHAUS [ IC-HAUS GMBH ]
