iC-LNB 18-BIT OPTO ENCODER
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 22/35
REQ
and a DATA byte. The DATA byte is not available in
iC-LNB and is thus not defined.
CS
SCLK
CS
OP
MOSI
SCLK
OP
SV 0-7 SV 8-15
...
MISO
OP
MOSI
8 cycles
OP
STATUS DATA
MISO
Figure 10: SDAD status
8 cycles
If only one slave is connected, the relevant SVALID bit
is placed at bit position 7 in the SVALID byte (SV0,
Figure 11).
Figure 12: REGISTER status/data
Read REGISTER (continuous)
REQ
The master transmits the OPCODE Read REGISTER
(cont.). Start address ADR, from which point data is to
be read, is transmitted in the 2nd byte. The slave im-
mediately outputs the OPCODE and address and then
transmits DATA1. The internal address counter is in-
cremented after each data package.
CS
SCLK
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OP
OP
MOSI
MISO
SV 0
8 cycles
SVALID vector
If an error occurs during register readout in continu-
ous mode, i.e. the address is invalid, the requested
data was not valid on data byte clocking, etc., the in-
ternal address counter is incremented no further and
the FAIL error bit is set in the status byte (Table 14).
Figure 11: SDAD status (one slave)
REGISTER status/data
The status of the last REGISTER communication or
the last data transmission can be queried using the
REGISTER status/data command. The STATUS byte
contains the information summarized in Table 14.
CS
SCLK
STATUS
OP
OP
ADR
ADR
MOSI
MISO
Bit
Name
Description of the status
report
DATA1 DATA2
...
7
ERROR
OPCODE invalid.
Sensor data was invalid
on readout
8 cycles
6..4
3
-
Reserved
DISMISS
FAIL
Address refused
Data request has failed
Figure 13: Read REGISTER (cont.)
2
1
BUSY
Slave is busy with a
request
Write to REGISTER (continuous)
0
VALID
DATA is valid
The master transmits the OPCODE Write to REGIS-
TER (cont.). Start address ADR, from which point suc-
cessive data DATA1-DATAn is to be written, is transmit-
ted in the 2nd byte. The slave immediately outputs the
OPCODE, address, and data at MISO. The slave incre-
ments its internal address counter after each DATAn
data package.
NB
Display logic: 1 = true, 0 = false
Table 14: SPI status information
All status bits are updated with each register access.
The ERROR bit is the exception to the rule; this bit
signals whether an error occurred during the last com-
munication with the SPI interface or not.
If an error occurs during a write to register in contin-
uous mode, i.e. the address is invalid, writing of the
The master transmits the OPCODE REGISTER sta- last address data has not finished, etc., the internal ad-
tus/data. iC-LNB immediately passes the OPCODE dress counter is incremented no further and the FAIL
on to MISO. iC-LNB then transmits the STATUS byte error bit is set in the status byte (Table 14).
ICHAUS [ IC-HAUS GMBH ]
