iC-LFH Series
HIGH-RESOLUTION LINEAR IMAGE SENSORS
Rev B1, Page 10/14
PIXEL 1
PIXEL 2
PIXEL 3
PIXEL 4
VDDA
NRCI
INTEGRATION
BNA
RESx
S&H
S&H
S&H
S&H
HOLD
ESH
READ
RD1
RD2
RD3
RD4
Figure 6: Pixel structure with resolution change and binning mode
Operation description Operation with the shutter function
Following an internal power-on reset the integration and Integration can be suspended at any time via pin ESH
hold capacitors are discharged. A high signal at SI and (asynchronous, global shutter), i.e. the photodiodes are
a rising edge at CLK triggers a readout cycle and with disconnected from their corresponding integration ca-
it a new integration cycle. Six clocks later the internal pacitor when ESH is high and the current integration
reset is done and the device is in integration mode. The capacitor voltages are maintained. If this pin is open or
readout of the analog pixel values starts with the 17th switched to GND, the pixel photocurrents are summed
clock pulse.
up by the integration capacitors until the next SI signal.
PINS
SI
CLK
ESH
VMIN
1
2
N-1
N
AO
INTERNAL
CLK NR
N+10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
N+15 N+16
1
2
SAMPLE
READ INT1
SAMPLE
READ READ INT0
INT
INT1
RESET
INT2
Figure 7: example integration and readout cycle
ICHAUS [ IC-HAUS GMBH ]
