SI4432 参数 Datasheet PDF下载

型号：	SI4432
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Si4430/31/32-B1

8.7. Low Duty Cycle Mode

The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available.

The basic operation of the low duty cycle mode is demonstrated in the figure below. If a valid preamble or sync

word is not detected the chip will return to sleep mode until the beginning of a new WUT period. If a valid preamble

and sync are detected the receiver on period will be extended for the low duty cycle mode duration (TLDC) to

receive all of the packet. The WUT period must be set in conjunction with the low duty cycle mode duration. The R

value (“Register 14h. Wake-up Timer Period 1”) is shared between the WUT and the TLDC. The ldc[7:0] bits are

located in “Register 19h. Low Duty Cycle Mode Duration.” The time of the TLDC is determined by the formula

below:

4  2

TLDC  ldc [7 : 0 ] 

32 .768

Figure 30. Low Duty Cycle Mode

Rev 1.0