Si4430/31/32-B1
8. Auxiliary Functions
8.1. Smart Reset
The Si4430/31/32 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both
a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce a
reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occur:
Initial power on, VDD starts from gnd: reset is active till VDD reaches V (see table);
RR
When VDD decreases below V for any reason: reset is active till VDD reaches V
;
RR
LD
A software reset via “Register 08h. Operating Mode and Function Control 2”: reset is active for time T
SWRST
On the rising edge of a VDD glitch when the supply voltage exceeds the following time functioned limit:
VDD nom.
VDD(t)
reset limit:
0.4V+t*0.2V/ms
actual VDD(t)
showing glitch
0.4V
Reset
TP
t
t=0,
reset:
VDD starts to rise
Vglitch>=0.4+t*0.2V/ms
Figure 26. POR Glitch Parameters
Table 15. POR Parameters
Parameter
Release Reset Voltage
Power-On VDD Slope
Low VDD Limit
Symbol
VRR
Comment
Min
0.85
0.03
0.7
Typ
Max
1.75
300
1.3
Unit
V
1.3
SVDD
VLD
tested VDD slope region
VLD<VRR is guaranteed
V/ms
V
1
Software Reset Pulse
Threshold Voltage
TSWRST
VTSD
k
50
470
us
0.4
0.2
16
V
Reference Slope
V/ms
ms
VDD Glitch Reset Pulse
TP
Also occurs after SDN, and
initial power on
5
40
The reset will initialize all registers to their default values. The reset signal is also available for output and use by
the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on
GPIO_1.
50
Rev 1.0
IBM [ IBM ]
