IBMN625404GT3B
IBMN625804GT3B
256Mb Double Data Rate Synchronous DRAM
Preliminary
Mode Register Operation
BA1 BA0 A12
A11 A10 A9
Operating Mode
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Address Bus
Mode Register
0*
0*
CAS Latency
Burst Length
A12 - A9
0
A8
0
A7
0
A6 - A0
Valid
Operating Mode
A3
Burst Type
Sequential
Interleave
Normal operation
Do not reset DLL
0
1
Normal operation
in DLL Reset
0
1
0
Valid
Vendor-Specific
Test Mode
0
0
1
VS**
−
−
−
Reserved
CAS Latency
Burst Length
A6
A5
0
A4
0
Latency
Reserved
Reserved
2
A2
0
A1
0
A0
0
Burst Length
0
0
0
0
1
1
1
1
Reserved
2
0
1
0
0
1
1
0
0
1
0
4
1
1
Reserved
Reserved
Reserved
2.5
0
1
1
8
0
0
1
0
0
Reserved
Reserved
Reserved
Reserved
0
1
1
0
1
1
0
1
1
0
1
1
Reserved
1
1
1
VS** Vendor Specific
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997B
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