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IBMN625405GT3B-8N 参数 Datasheet PDF下载

IBMN625405GT3B-8N图片预览
型号: IBMN625405GT3B-8N
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 64MX4, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 79 页 / 1328 K
品牌: IBM [ IBM ]
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IBMN625404GT3B  
IBMN625804GT3B  
Preliminary  
256Mb Double Data Rate Synchronous DRAM  
Operations  
Bank/Row Activation  
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank  
must be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and  
BA1 (see Activating a Specific Row in a Specific Bank), which decode and select both the bank and the row  
to be activated. After opening a row (issuing an Active command), a Read or Write command may be issued  
to that row, subject to the t  
specification. A subsequent Active command to a different row in the same  
RCD  
bank can only be issued after the previous active row has been “closed” (precharged). The minimum time  
interval between successive Active commands to the same bank is defined by t . A subsequent Active com-  
RC  
mand to another bank can be issued while the first bank is being accessed, which results in a reduction of  
total row-access overhead. The minimum time interval between successive Active commands to different  
banks is defined by t  
.
RRD  
Activating a Specific Row in a Specific Bank  
CK  
CK  
HIGH  
CKE  
CS  
RAS  
CAS  
WE  
RA = row address.  
BA = bank address.  
RA  
BA  
A0-A12  
BA0, BA1  
Don’t Care  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
29L0011.E36997B  
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