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IBMN625405GT3B-8N 参数 Datasheet PDF下载

IBMN625405GT3B-8N图片预览
型号: IBMN625405GT3B-8N
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 64MX4, 0.8ns, CMOS, PDSO66, 0.400 INCH, PLASTIC, TSOP2-66]
分类和应用: 动态存储器双倍数据速率光电二极管内存集成电路
文件页数/大小: 79 页 / 1328 K
品牌: IBM [ IBM ]
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IBMN625404GT3B  
IBMN625804GT3B  
256Mb Double Data Rate Synchronous DRAM  
Preliminary  
Operating Mode  
The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero,  
and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a Mode Register Set command  
with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode  
Register Set command issued to reset the DLL should always be followed by a Mode Register Set command  
to select normal operating mode.  
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and  
reserved states should not be used as unknown operation or incompatibility with future versions may result.  
CAS Latencies  
CAS Latency = 2, BL = 4  
CK  
CK  
Read  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
CL=2  
DQS  
DQ  
CAS Latency = 2.5, BL = 4  
CK  
CK  
Read  
NOP  
NOP  
NOP  
NOP  
NOP  
Command  
CL=2.5  
DQS  
DQ  
Shown with nominal t , t  
, and t  
.
DQSQ  
Don’t Care  
AC DQSCK  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
29L0011.E36997B  
1/01  
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