Preliminary
IBMN312804CT3
IBMN312404CT3
128Mb Synchronous DRAM - Die Revision B
IBMN312164CT3
Block Diagram
CKE
CKE Buffer
Row Decoder
Column Decoder
Column Decoder
Row Decoder
Cell Array
Memory Bank 0
Cell Array
Memory Bank 1
CLK
CLK Buffer
Sense Amplifiers
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
BS0
BS1
A10
Sense Amplifiers
Data Input/Output Buffers
DQM
Column Decoder
Cell Array
Memory Bank 3
Sense Amplifiers
Address Buffers (14)
Control Signal
Generator
Data Control Circuitry
DQ
0
DQ
X
Refresh
Counter
Column
Address
Counter
Mode Register
Column Decoder
Command Decoder
Row Decoder
Row Decoder
CS
RAS
CAS
WE
Cell Array
Memory Bank 2
Sense Amplifiers
Cell Array, per bank, for 8Mb x 4 DQ: 4096 Row x 2048 Col x 4 DQ (DQ0-DQ3).
Cell Array, per bank, for 4Mb x 8 DQ: 4096 Row x 1024 Col x 8 DQ (DQ0-DQ7).
Cell Array, per bank, for 2Mb x 16 DQ: 4096 Row x 512 Col x 16 DQ (DQ0-DQ15).
06K7582.H03335A
01/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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