IBMN312164CT3
IBMN312804CT3
IBMN312404CT3
Preliminary
128Mb Synchronous DRAM - Die Revision B
Mode Register Operation (Address Input For Mode Set)
Address
Bus (Ax)
BS1 BS0
A11 A10 A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
Mode
Register(Mx)
Operation Mode
CAS Latency
Burst Length
Burst Type
M3
0
Type
Sequential
Interleave
1
Operation Mode
Burst Length
M13 M12 M11 M10 M9 M8 M7
Mode
Length
0
0
0
0
0
0
0
Normal
M2 M1 M0
Sequential Interleave
Multiple Burst
with
Single Write
0
0
0
0
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
CAS Latency
M6
0
M5 M4
Latency
Reserved
Reserved
2
Reserved Reserved
Reserved Reserved
Reserved Reserved
Reserved Reserved
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
3
1
Reserved
Reserved
Reserved
Reserved
1
1
1
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 7 of 66
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