IBMN312164CT3
IBMN312404CT3
IBMN312804CT3
128Mb Synchronous DRAM - Die Revision B
Preliminary
Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. There is no CAS latency
required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same
clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subse-
quent rising clock edge until the burst length is completed. When the burst has finished, any additional data
supplied to the DQ pins will be ignored.
Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DIN A
0
DIN A
DIN A
DIN A
3
DQs
1
2
: “H” or “L”
The first data element and the Write
are registered on the same clock edge.
Extra data is masked.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previ-
ous burst is interrupted, the remaining addresses are overridden by the new address and data will be written
into the device until the programmed burst length is satisfied.
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK
NOP
WRITE A
WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
1 CK Interval
DIN A
DIN B
0
DIN B
DIN B
DIN B
3
DQs
0
1
2
©IBM Corporation. All rights reserved.
06K7582.H03335A
01/01
Use is further subject to the provisions at the end of this document.
Page 14 of 66
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