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IBMN312404CT3B-75A 参数 Datasheet PDF下载

IBMN312404CT3B-75A图片预览
型号: IBMN312404CT3B-75A
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54]
分类和应用: 时钟动态存储器光电二极管内存集成电路
文件页数/大小: 66 页 / 2855 K
品牌: IBM [ IBM ]
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IBMN312164CT3  
IBMN312404CT3  
IBMN312804CT3  
128Mb Synchronous DRAM - Die Revision B  
Preliminary  
Clock and Clock Enable Parameters  
-75H  
-75D  
-75A  
-260  
-360  
-10  
Symbol  
Parameter  
Units Notes  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tCK3 Clock Cycle Time, CAS Latency = 3 7.5 1000 7.5 1000 7.5 1000 10 1000 10 1000 10 1000 ns  
7.5 1000  
tCK2 Clock Cycle Time, CAS Latency = 2  
10ns 1000 10 1000 15 1000 14 1000 ns  
10 1000  
Clock Access Time, CAS Latency =  
3
tAC3 (A)  
6
6
7
8
9
9
ns  
ns  
ns  
ns  
1
1
2
2
Clock Access Time, CAS Latency =  
2
tAC2 (A)  
Clock Access Time, CAS Latency =  
3
tAC3 (B)  
5.4  
5.4  
5.4  
5.4  
Clock Access Time, CAS Latency =  
2
tAC2 (B)  
6
9
tCKH Clock High Pulse Width  
tCKL Clock Low Pulse Width  
tCES Clock Enable Set-up Time  
tCEH Clock Enable Hold Time  
2.5  
2.5  
1.5  
0.8  
0
2.5  
2.5  
1.5  
0.8  
0
2.5  
2.5  
1.5  
0.8  
0
3
3
10  
10  
3
3
10  
10  
3
3
10  
10  
ns  
ns  
ns  
ns  
ns  
ns  
2
2
3
1
1
1
tSB  
tT  
Power down mode Entry Time  
Transition Time (Rise and Fall)  
7.5  
10  
7.5  
10  
7.5  
10  
0
0
0
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.  
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.  
Common Parameters  
-75H  
-75D  
-75A  
-260  
-360  
-10  
Symbol  
Parameter  
Units Notes  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
tCS Command Setup Time  
tCH Command Hold Time  
1.5  
0.8  
1.5  
0.8  
1.5  
0.8  
15  
1.5  
0.8  
1.5  
0.8  
20  
2
1
2
1
3
1
ns  
ns  
ns  
ns  
tAS  
Address and Bank Select Set-up Time 1.5  
2
2
3
tAH Address and Bank Select Hold Time  
tRCD RAS to CAS Delay  
tRC Bank Cycle Time  
0.8  
15  
60  
1
1
1
20  
70  
20  
70  
28  
84  
ns  
ns  
1
1
1
1
1
60  
67.5  
tRAS Active Command Period  
tRP Precharge Time  
45 100K 45 100K 45 100K 50 100K 50 100K 56 100K ns  
15  
15  
1
15  
15  
1
20  
15  
1
20  
20  
1
20  
20  
1
14  
20  
1
ns  
ns  
tRRD Bank to Bank Delay Time  
tCCD CAS to CAS Delay Time  
CK  
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:  
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).  
Mode Register Set Cycle  
-75H  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.  
15 15 15 20 20 20  
-75D  
-75A  
-260  
-360  
-10  
Symbol  
Parameter  
Units  
ns  
tRSC Mode Register Set Cycle Time  
©IBM Corporation. All rights reserved.  
06K7582.H03335A  
01/01  
Use is further subject to the provisions at the end of this document.  
Page 38 of 66  
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