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IBM13N8644HCC-10T 参数 Datasheet PDF下载

IBM13N8644HCC-10T图片预览
型号: IBM13N8644HCC-10T
PDF下载: 下载PDF文件 查看货源
内容描述: [Synchronous DRAM Module, 8MX64, 9ns, CMOS, DIMM-168]
分类和应用: 时钟动态存储器内存集成电路
文件页数/大小: 19 页 / 361 K
品牌: IBM [ IBM ]
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IBM13N8644HCC  
IBM13N8734HCC  
8M x 64/72 One-Bank Unbuffered SDRAM Module  
Serial Presence Detect (Part 1 of 2)  
Serial PD Data Entry (Hexa-  
Byte #  
Description  
SPD Entry Value  
Notes  
decimal)  
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production  
Total Number of Bytes in Serial PD device  
Fundamental Memory Type  
128  
80  
256  
08  
SDRAM  
04  
Number of Row Addresses on Assembly  
Number of Column Addresses on Assembly  
Number of DIMM Banks  
12  
0C  
09  
9
1
01  
8M x 64  
8M x 72  
x64  
4000  
4800  
01  
6 - 7  
Data Width of Assembly  
x72  
8
9
Voltage Interface Level of this Assembly  
SDRAM Device Cycle Time at CL=3  
LVTTL  
10.0ns  
A0  
60  
-260, -360  
-10  
6.0ns  
1
10  
11  
SDRAM Device Access Time from Clock at CL=3  
DIMM Configuration Type  
7.0ns  
70  
8M x 64  
8M x 72  
Non-Parity  
00  
ECC  
02  
12  
13  
Refresh Rate/Type  
SR/1x(15.625us)  
80  
Primary SDRAM Device Width  
x8  
08  
8M x 64  
8M x 72  
N/A  
00  
14  
Error Checking SDRAM Device Width  
x8  
08  
15  
16  
17  
18  
19  
20  
21  
SDRAM Device Attr: Min Clk Delay, Random Col Access  
SDRAM Device Attributes: Burst Lengths Supported  
SDRAM Device Attributes: Number of Device Banks  
SDRAM Device Attributes: CAS Latencies Supported  
SDRAM Device Attributes: CS Latency  
1 Clock  
01  
1,2,4,8, Full Page  
8F  
4
04  
2, 3  
06  
0
0
01  
SDRAM Device Attributes: WE Latency  
01  
SDRAM Module Attributes  
Unbuffered  
00  
Wr-1/Rd Burst, Precharge All,  
Auto-Precharge, VDD +/- 10%  
22  
SDRAM Device Attributes: General  
0E  
-260  
-360  
-10  
10.0ns  
15.0ns  
15.0ns  
6.0ns  
9.0ns  
8.0ns  
N/A  
A0  
F0  
F0  
60  
90  
80  
00  
00  
14  
1E  
14  
14  
14  
1E  
32  
3C  
23  
Minimum Clock Cycle at CL=2  
-260  
-360  
-10  
Maximum Data Access Time (tAC) from Clock at  
CL=2  
1
24  
25  
26  
Minimum Clock Cycle Time at CL=1  
Maximum Data Access Time (tAC) from Clock at CL=1  
N/A  
-260, -360  
-10  
20ns  
30ns  
20ns  
20ns  
20ns  
30ns  
50ns  
60ns  
Minimum Row Precharge Time (tRP  
)
27  
28  
29  
30  
-260, -360  
-10  
Minimum Row Active to Row Active delay (tRRD  
)
-260, -360  
-10  
Minimum RAS to CAS delay (tRCD  
)
-260, -360  
-10  
Minimum RAS Pulse width (tRAS  
)
1. See the AC output load circuit in the AC Characteristics section below  
2. cc = Checksum Data byte, 00-FF (Hex)  
3. “R” = Alphanumeric revision code, A-Z, 0-9  
4. rr = ASCII coded revision code byte “R”  
5. yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex)  
6. ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex)  
7. ss = Serial number data byte, 00-FF (Hex)  
19L7295.E93875B  
12/99  
©IBM Corporation. All rights reserved.  
Use is further subject to the provisions at the end of this document.  
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