IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Operating, Standby, and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
Speed/Organization
Parameter
Symbol
Test Condition
Units Notes
-260, -360/
x64
-260, -360/
-10/x64
440
-10/x72
495
x72
Operating Current
= t (min), t = min
t
RC
RC
CK
I
1 Bank operation
560
630
mA
1, 2
CC1
Active-Precharge command
cycling without Burst operation
CKE0 ≤ V (max), t = min,
IL
CK
I
8
8
8
9
9
9
9
mA
mA
mA
mA
mA
CC2P
S0, S2 =V (min)
IH
Precharge Standby Current in
Power Down Mode
CKE0 ≤ V (max), t = Infinity,
IL
CK
I
8
CC2PS
S0, S2 =V (min)
IH
CKE0 ≥ V (min), t = min,
IH
CK
I
200
48
240
200
48
240
225
54
270
225
54
270
3
4
3
CC2N
S0, S2 =V (min)
IH
Precharge Standby Current in
Non-Power Down Mode
CKE0 ≥ V (min), t = Infinity,
IH
CK
I
CC2NS
S0, S2 =V (min)
IH
CKE0 ≥ V (min), t = min,
IH
CK
I
CC3N
S0, S2 =V (min)
IH
No Operating Current
(Active state: 4 bank)
CKE0 ≤ V (max), t = min,
IL
CK
I
S0, S2 =V (min)
24
24
27
27
mA
mA
5
CC3P
IH
(Power Down Mode)
t
= min,
CK
Read/write command cycling,
multiple banks active,
Burst Operating Current
I
720
720
810
810
2, 6
CC4
gapless data, BL = 4
t
= min, t = t (min),
RC RC
CK
Auto (CBR) Refresh Current
Self Refresh Current
I
I
1120
8
880
8
1260
9
990
9
mA
mA
µA
CC5
CC6
CBR command cycling
CKE0 ≤ 0.2V
Serial PD Device Standby Cur-
rent
I
V
= GND or V
DD
30
30
30
30
7
8
SB
IN
Serial PD Device Active Power
Supply Current
SCL Clock Frequency =
100KHz
I
1
1
1
1
mA
CCA
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t and t
.
RC
CK
Input signals are changed up to three times during t (min).
RC
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during t
.
ck(min)
7. V = 3.3V
DD
8. Input pulse levels V x 0.1 to V x 0.9, input rise and fall times 10ns, input and output timing levels V x 0.5, output load 1 TTL
DD
DD
DD
gate and CL=100pf.
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 19
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