Preliminary
IBMB3N32644HCB
IBMB3N32734HCB
32M x 64/72 One-Bank Unbuffered SDRAM Module
Input/Output Functional Description
Symbol
CK0, CK2
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Active
High
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their
associated clock.
Activates the CK0 and CK2 signals when high and deactivates them when low. By deac-
tivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
CKE0
Input
Level
S0,S2
RAS, CAS
WE
BA0, BA1
Input
Pulse
Enables the associated SDRAM command decoder when low and disables the command
Active Low decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
Active Low
—
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 define the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-
charge.
Data and Check Bit Input/Output pins operate in the same manner as on conventional
DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sam-
pled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a byte mask by allowing input data to be written if it is low but blocks the Write operation
if DQM is high.
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
Input
Input
Pulse
Level
A0 - A9
A10/AP
A11, A12
Input
Level
—
DQ0 - DQ63,
CB0 - CB7
Input
Output
Level
—
DQMB0 -
DQMB7
Input
Pulse
Active
High
SA0 - SA2
Input
Level
—
SDA
Input
Output
Level
—
Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.
On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied
to ground through a 47K ohm pull-down resistor.
Power and ground for the module.
SCL
Input
Pulse
—
WP
V
DD
, V
SS
Input
Level
Active
High
Supply
06K3671.H01574A
04/01
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 18
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