IBM42M10SNYAA20
IBM42M10LNYAA10
1063 Mbps Gigabit Link Module - No OFC
Block Diagram
Lck_Ref
En_CDet
Fiber
Input
Photo-
detector
Shift Register
Postamp
&
MUX
Rx
PLL
Com_Det
Rx[00:19]
Clock
Generator
RBC[0:1]
Transition
Detector
Transition
Detector
L_Unuse
Loss of
Light
Detector
Fiber
Output
Laser
AC Drive
Shift Register
Tx[00:19]
DC Drive
Tx PLL
EWrap
Fault
Sense
TBC
Fault
Transmit Section
The 20-bit transmit data enters the shift register and is clocked out at 1062.5 Mbps to the serial output pins
and the multiplexer. The AC Drive modulates the laser with the data from the Serial Input pins or the serial-
ized version of the Transmit Data. The Transmit Phase Locked Loop (Tx PLL) generates the internal 1062.5
MHz clock for the shift register from the 53.125 MHz Transmit Byte Clock provided by the system. The DC
Drive maintains the laser at the correct preset power level. Safety circuits in the DC Drive will shut off the
laser if a fault is detected. The multiplexer is used to route the serialized data to the Receive Section while in
wrap mode.
Receive Section
The incoming, modulated optical signal is received by the photoreceiver. The Receive PLL (Rx PLL) phase
locks a 1062.5 MHz clock to the data and sends the data and clock to the shift register (S/R) to be deserial-
ized. The S/R has a byte synchronization detector that recognizes a unique Comma Character so that com-
plete bytes can be unloaded from the S/R without being fragmented. The Clock Generator creates two
complementary phases of a 53.125 MHz clock for use by the host system to latch the Receive Data.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
GLM1063N.03
November 29, 2000
Page 4 of 26
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