IBM42M10SCYAA10
IBM42M10LCYAA20
1063Mb/s Gigabit Link Module
Block Diagram
Lck_Ref
En_CDet
Fiber
Input
Photo-
detector
Shift Register
Postamp
&
MUX
Rx
PLL
Clock
Generator
Com_Det
Rx[00:09]
RBC[0:1]
Transition
Detector
Transition
Detector
Open
Fibre
Control
L_Unuse
Fault
Fiber
Output
Laser
AC Drive
Shift Register
Tx[00:09]
DC Drive
Tx PLL
EWrap
Fault
Sense
TBC
Transmit Section
The 20-bit transmit data enters the shift register and is clocked out at 1062.5Mbit/s to the serial output pins
and the multiplexer. The AC Drive modulates the laser with the data from the Serial Input pins or the serial-
ized version of the Transmit Data. The Transmit Phase Locked Loop (Tx PLL) generates the internal
1062.5MHz clock for the shift register from the 53.125MHz Transmit Byte Clock provided by the system. The
DC Drive maintains the laser at the correct preset power level. Safety circuits in the DC Drive will shut off the
laser if a fault is detected. The multiplexer is used to route the serialized data to the Receive Section while in
wrap mode.
Receive Section
The incoming, modulated optical signal is received by the photoreceiver. The Receive PLL (Rx PLL) phase
locks a 1062.5MHz clock to the data and sends the data and clock to the shift register (S/R) to be deserial-
ized. The S/R has a byte synchronization detector that recognizes a unique comma character so that
complete bytes can be unloaded from the S/R without being fragmented. The Clock Generator creates two
complementary phases of a 53.125MHz clock for use by the host system to latch the Receive Data.
Page 4 of 30
glm1063.02.fm.02
Feb. 15, 2000
IBM [ IBM ]
