IBM39STB032xx
IBM39STB034xx
Preliminary
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
Peripheral Subsystem
IBM STB03xxx
Peripheral Subsystem
GPT / PWM
IEEE 1284
SmartCard (2)
IIC (2)
OPB
Bridge
16550 Serial Com
Infrared Serial Com
GPIO
Serial Control Port
Modem Interface
General Purpose Timer
The General Purpose Timer (GPT) is an on-chip peripheral bus (OPB) function that provides a separate time
base counter and additional system timers beyond those defined in the PPC405B3.
Three Inter-Character (IC) time-out timers are also implemented in this functional unit in the GPT. These tim-
ers receive the count signal inputs from other units they are timing. Each timer is a 10-bit down counter
loaded with a programmable value (TOUT) upon the active edge of the count signal input. Once loaded, the
IC timer counts down TOUT number of TCLK cycles until it reaches zero (that is, when the IC timer has
expired). When a timer expires, it sets its corresponding bit in the IC interrupt status register.
There is a separate time base inside the GPT, distinct from the time base within the PPC405B3. Two event
timers capture unique input events and there are two compare timers with unique outputs. Separately config-
urable and programmable synchronization controls edge detection and output levels. There are two reset
inputs, one for the entire GPT unit, and one for the time base.
Pulse Width Modulation
The pulse width modulation (PWM) function produces two square wave outputs with a variable duty cycle
under program control. The duty cycle varies from 100 percent to zero percent in steps of 1/256. There is a
control register with two bits for each PWM. This register controls the active status of the PWM, and deter-
mines what its inactive output level should be. When the PWM control register is set to disable a PWM, the 8-
bit period counter will be inactive to minimize power.
The pulse width modulation portion of the GPT contains two identical blocks, each containing an 8-bit pro-
grammable and reloadable down counter and control logic. A time-base generator that is a free-running
counter (TCLK based) generates the frequency of the pulse-width modulated output.
STB03_sds_041800.fm.01
April 18, 2000
Architecture and Subsystem Information
Page 13 of 55
IBM [ IBM ]
