Preliminary
IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
the overhead associated with the controller setup is minimal compared to the time it would take to move data
using program control load and store instructions.
Each DMA channel has an independent set of registers for data transfer. The registers store data for control,
source address, destination address, and transfer count. Each channel also supports chained DMA opera-
tions, therefore every channel also includes a chained count register in which case source address registers
function as chained address registers. All DMA channels report their status to the DMA execution unit.
The DMA controller also supports:
• Internal DMA channels for 1284 parallel port, Smart Card interface, 16550 serial communications control-
ler, infrared communications controller, etc.
• 16- and 32-bit peripherals (on-chip peripheral bus and external)
• 32-bit addressing
• Address increment or decrement
• Internal data buffering capability
• Memory-mapped peripherals
Processor Local Bus
The Processor Local Bus (PLB) interfaces directly with the PPC405B3 and the other major subsystems (see
masters and the external memory interfaces for ROM, Flash, and SDRAM, etc. The STB03xxx PLB architec-
ture includes a crossbar switch to present both memory interfaces as flat, shared memory spaces.
External Bus Interface Unit
The External Bus Interface Unit (EBIU) expands the local bus to transfer data between the PLB and a wide
range of memory and peripheral devices attached to the external bus (see the following list). The EBIU can
control up to eight devices or banks or regions of FLASH memory (128 MB), and a low latency maximizes
system performance.
The EBIU supports:
• A direct connect SRAM/ROM/PIA interface for
- up to eight SRAM/ROM/PIA banks with programmable address select
- programmable or device-paced wait states
- burst mode (BME) and single-cycle transfers
• 16- and 32-bit byte addressable bus width
• Programmable target word first or sequential cache line fills
• IDE interface
• supports ATA-3 Mode 4 register and PIO transfers
• supports Mode 2 Multiword DMA transfers (see ANSI X3.298-1997, AT Attachment-3 Interface (ATA-
3))
• DVB Common Interface Support
• External bus master with support for device master and master/slave
• Common bank-specific programmability
• Device-paced ready input
STB03_sds_041800.fm.01
April 18, 2000
Architecture and Subsystem Information
Page 7 of 55
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