IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
Preliminary
Note 1. MODEM_CLK can be configured to send and receive data on the rising or falling clock edge.
Note 2. MODEM_FR can be an input or an output.
Serial Control Port Timing
Internal
SYSCLK
t2
t1
Output
SMC_CLK
SMC_TXD
t3
t4
Output
Input
t6
t5
SMC_RXD
SCP Timing Values
Symbol
Parameter
Min
Max
80.8
12
Units
T
T
T
T
T
T
SMC_clk period
ns
ns
ns
ns
ns
ns
1
2
3
4
5
6
Output valid time
Output valid time
Output hold time
Input setup time
Input hold time
13
4
10
3
Note: This timing diagram assumes the CI bit in the SCP SPMODE register is set to 0. If CI is set to 1, the LK
signal is inverted.
Electrical Information
Page 50 of 55
STB03_sds_041800.fm.01
April 18, 2000
IBM [ IBM ]
