IBM39STB032xx
IBM39STB034xx
STB032xx and STB034xx Digital Set-Top Box Integrated Controllers
Preliminary
IEEE 1284 Parallel Port
The IEEE 1284 Parallel Port is implemented as either the host side or peripheral side of the parallel port data
1
2
bus. The parallel port bidirectional interface supports IEEE Std. 1284 extended capability port (ECP) , byte ,
3
4
nibble , and compatibility modes of operation. The parallel port also monitors IEEE Std. 1284 negotiation
mode events, which allows the host to determine the capabilities of an attached peripheral and to set the
interface into one of the four operational modes. The parallel port supports byte-wide FIFO but does not sup-
port Enhanced Parallel Port (EPP) mode. Two Direct Memory Access (DMA) channels for transmit and
receive allow independent data transfers from other peripherals. The IEEE 1284 Parallel Port is compatible
with existing parallel port hosts, and an Inter-Character Time-out Facility provides support with the
GPT/PWM.
Inter-Integrated Circuit (IIC) Units
Two unique IIC units are used to provide two independent IIC interfaces and provide a simple to use, highly
programmable interface between the OPB and the industry standard IIC serial bus. They provide full man-
2
agement of all IIC bus protocols, compliant with Phillips Semiconductors I C Specification, dated 1995, and
support a fixed V IIC interface. These IICs can be programmed to operate as master, as slave, or as both
DD
master and slave on the IIC interface. In addition to sophisticated IIC bus protocol management, the IICs pro-
vide full data buffering between the OPB and the IIC bus.
The IIC units offer 5 V tolerant I/O for both 100- and 400-kHz operation with 8-bit data transfers and 7-bit and
10-bit address decode/generation. There is one programmable interrupt request signal, two independent 4 x
1-byte data buffers, and 12 memory-mapped, fully programmable configuration registers.
Smart Card Interface Units
The Smart Card Interface Units handle communications between an Integrated Circuit Card and the host
CPU. These 5 V tolerant I/O devices have a software-based control structure and are designed for use with
asynchronous transmissions. They feature hardware activation/deactivation and reset with software overrides
and byte-wide FIFO support. They are compatible with ISO/IEC 7816-3 and support T0 and T1 protocols. The
Interface Units support 2-channel DMA with 8-bit memory-mapped registers and hardware error checking. An
Inter-Character Time-out Facility provides timing support from the GPT/PWM.
16550 Serial Communication Controller
The 16550 Serial Communication Controller is a universal asynchronous receiver/transmitter (UART) with
FIFOs, and is compatible with the 16550 part numbers manufactured by National Semiconductor (NS) Corpo-
ration. It is also compatible with National Semiconductor 16450 (non-FIFO version). Serial interface charac-
teristics are fully programmable with complete modem control functions and status reporting capability. The
controller supports:
• 5-, 6-, 7-, or 8-bit characters
• Even, odd, or no parity bit generation and detection
• 1-, 1.5-, or 2-stop-bit generation
• Variable baud rate and a programmable baud rate generator
1. ECP refers to the extended capability port. An asynchronous, byte-wide, bidirectional channel.
2. Byte refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host.
3. Nibble refers to an asynchronous, reverse (peripheral-to-host) channel, under the control of the host.
4. Compatibility refers to an asynchronous, byte-wide forward (host-to-peripheral) channel.
Architecture and Subsystem Information
Page 14 of 55
STB03_sds_041800.fm.01
April 18, 2000
IBM [ IBM ]
