IBM3229P2035
IBM Packet Routing Switch Serial Interface Converter
Advance
Considering an LU, the CRC byte when inserted is computed from the end of the previous idle packet sent on
the DASL interface (end of cell boundary, CRC byte), and up to the current idle packet last byte (byte
preceding CRC location).
3.6.3.3 Synchronization Packets Format
Synchronization packets synchronize DASLs. Characteristics of this packet allows the remote DASL oper-
ating as receiver to recover bit transition and packet delineation (packet clock recovery). Synchronization
packet format is as follows:
Master LU
Slave LU
Slave LU
Slave LU
x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’33’
x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’33’
x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’33’
x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’CC’ x’33’
3.6.3.4 Data Packets
• Data Packet Format Switch 8x8 and 16x16
Master LU
Slave LU
Slave LU
Slave LU
PQ
D
BM0
D
BM1
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
• Data Packet Format Switch 32x32
Master LU
Slave LU
Slave LU
Slave LU
PQ
D
BM0
D
BM1
D
BM2
D
BM3
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
3.6.4 Egress Data Aligned Serial Link (DASL) Interface (EDI)
The IBM Packet Routing Switch Serial Interface Converter’s packets have a fixed length of 64 - 80 bytes
(based on the setting in the configuration register) and are mapped on 4-byte words. Therefore a new packet
is received every 16 to 20 clock cycles from the DASL. When a complete packet has been received, the 16 to
20 words are transferred to the egress FIFO.
The EDI analyzes the IBM 24.8 G Packet Routing Switch (switch) packet header from the master LU to indi-
cate the presence of an idle packet or data packet and the packet priority. Idle packets are discarded when
received, (no packet write request is presented to the egress FIFO). The EDI block also checks the LU CRC
(mapped into Idle Packets LU trailer). When an error is detected, the converter interrupt line is asserted (if
checker enabled) and the Idle CRC error counter is incremented.
The EDI checks switch header parity. An error count is incremented when an error is detected and the
processor interruption line is asserted (may be masked). Optional "error" packet discard function is provided.
The EDI performs switch grant extraction from the switch packet header. A grant information bit map is
carried into the switch output packet header and is reported per priority. Therefore grant information is
refreshed over four packet periods (if the four priorities are in use) for a given priority. A flywheel counter
mapped into the Idle Packet Qualifier synchronizes the converter with the switch counter.
Functional Description
Page 38 of 154
prssi.02.fm
March 1, 2001
IBM [ IBM ]
