IBM3009K2672
IBM SONET/SDH Framer
Chiplet Interrupt Request and Mask Registers
The chiplet interrupt request registers indicate pending interrupt requests from individual chiplets. An active
bit of these registers is reset by removing the cause for the request in the corresponding chiplet or by mask-
ing the active IRQ bit(s) in the chiplet; therefore, these registers are read-only.
For each bit position: 0: No chiplet interrupt request pending
1: Chiplet has pending interrupt request(s)
The chiplet interrupt request mask register bits control the propagation of a chiplet interrupt request to the
SONET/SDH framer interrupt output pin. The mask registers allow read and write access.
For each bit position: 0: The corresponding interrupt request bit is masked (DEFAULT)
1: The corresponding interrupt request bit is active (for IRMGP1, the corresponding
interrupt request bit activates the SONET/SDH framer Interrupt)
2.1: IRQGP1, IRMGP1 [3810 H Request, 3818 H Mask]
Signal Name
FElocHS
Bits
0
Access
R
Default
0
Description
Pending handshaking error active. This bit is set when a bit in the
HShake1 register and its corresponding interrupt mask bit in the HSMask1
register are both set to ‘1’.
Pending clock status error active. This bit is set when a bit in the ClkStat1
register and its corresponding interrupt mask bit in the ClkMask1 register
are both set to ‘1’.
FElocCS
1
R
0
Reserved
Reserved
IRQGP5
IRQGP4
IRQGP3
IRQGP2
2
3
4
5
6
7
R
R
R
R
R
R
0
0
0
0
0
0
Reserved
Reserved
Pending IRQ active in IRQGP5 register
Pending IRQ active in IRQGP4 register
Pending IRQ active in IRQGP3register
Pending IRQ active in IRQGP2 register
2.2: IRQGP2, IRMGP2 [3811 H Request, 3819 H Mask]
Signal Name
Bits
Access
Default
Description
IRQPT4
IRQPT3
IRQPT2
IRQPT1
IRQIR2
IRQIR1
IRQIT2
IRQIT1
0
1
2
3
4
5
6
7
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
IRQ from PH_Tx4
IRQ from PH_Tx3
IRQ from PH_Tx2
IRQ from PH_Tx1
IRQ from ACI_Rx2
IRQ from ACI_Rx1
IRQ from ACI_Tx2
IRQ from ACI_Tx1
ssframer.01
8/27/99
Register Descriptions
Page 119 of 279
IBM [ IBM ]
