IBM3009K2672
IBM SONET/SDH Framer
Chiplet Reset Registers
The bits of the chiplet reset registers control the enabling and disabling of complete chiplets.
For each bit position: 0: Reset inactive for this chiplet
1: Reset active (chiplet is disabled; DEFAULT)
1.1: RESGP1 [3800 H]
Signal Name
ResPT4
ResPT3
ResPT2
ResPT1
ResIR2
Bits
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
Description
1
1
1
1
1
1
1
1
Reset to chiplet PH_Tx4
Reset to chiplet PH_Tx3
Reset to chiplet PH_Tx2
Reset to chiplet PH_Tx1
Reset to chiplet ACI_Rx2
Reset to chiplet ACI_Rx1
Reset to chiplet ACI_Tx2
Reset to chiplet ACI_Tx1
1
2
3
4
ResIR1
5
ResIT2
6
ResIT1
7
1.2: RESGP2 [3801 H]
Signal Name
Bits
Access
Default
Description
ResHT4
ResHT3
ResHT2
ResHT1
ResPR4
ResPR3
ResPR2
ResPR1
0
1
2
3
4
5
6
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Reset to chiplet ACH_Tx4
Reset to chiplet ACH_Tx3
Reset to chiplet ACH_Tx2
Reset to chiplet ACH_Tx1
Reset to chiplet PH_Rx4
Reset to chiplet PH_Rx3
Reset to chiplet PH_Rx2
Reset to chiplet PH_Rx1
Register Descriptions
Page 116 of 279
ssframer.01
8/27/99
IBM [ IBM ]
