Datasheet
PowerPC 970FX RISC Microprocessor
Table 4-2. Pinout Listing for the CBGA Package (Page 3 of 5)
I/O
Signal Name
Pin Number
Active
Low
—
Notes
5
PI/PO
Input
GND
INT_B
AB19
T2
KVPRBGND
KVPRBVDD
6
6
Test Points
V
DD
R2
—
Test Points
LSSDMODE
AB5
U19
High
High
High
High
High
Low
High
—
Input
4
4
LSSD_SCAN_ENABLE
LSSD_STOP_ENABLE
LSSD_STOPC2_ENABLE
Input
AD11
AD8
Input
4
Input
4
LSSD_STOPC2STAR_ENABLE AD7
Input
4
MCP_B
AD18
Input
—
—
10
10
—
—
—
7
PLL_LOCK
PLL_MULT
PLL_RANGE(1:0)
PLLTEST
T20
Output
Input
AA8
AA9, AB7
—
Input
W22
High
—
Input
PLLTESTOUT
PROCID(0:2)
PSRO_ENABLE
PSRO0
T19
Output
Input
L19, M19, M18
—
V5
—
—
V23
—
Output
Input
—
—
—
—
—
—
PSYNC
AA10
—
PSYNC_OUT
PULSE_SEL(0:2)
QACK_B
AD14
—
Output
Input
AC9, AB11, AC10
—
V21
Low
Low
Input
QREQ_B
AB12
Output
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal system operation.
DD
2. These pins are reserved for potential future use.
3. TCK must be tied high or low for normal system operation. If used, TDI, TMS, and TRST_B must be pulled up to OV
.
DD
4. These are test signals for factory use only and must be pulled down with a 10 kΩ resistor to GND for normal system operation.
5. I = Input, O = Output, PI = Processor Interface Input, PO = Processor Interface Output. For additional information, see the Pow-
erPC 970FX RISC Microprocessor Users Manual.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point immedi-
ately behind the module. They should not be connected to GND and V planes.
DD
7. PSRO_ENABLE, Z_OUT, Z_SENSE, SPARE_GND, and SPARE2 must be tied to GND for correct operation.
8. CKTERM_DIS high disables SYSCLK termination.
9. If GPULDBG = ‘1’ during HRESET transition from low to high: Run power-on reset (POR) in debug mode and stop after each POR
instruction.
If GPULDBG = ‘0’ during HRESET transition from low to high: Run POR once in automatic mode without stopping after each POR
instruction.
Toggling GPULDBG from ‘1’ to ‘0’ later will finish POR debug mode and continue without stopping after each instruction.
10. The PLL_MULT and PLL_RANGE bits can be overwritten by Joint Test Action Group (JTAG) commands, and the BUS_CFG bits
can be changed by scan communication (SCOM) commands during the POR sequence. See the PowerPC 970FX Power On
Reset Application Note for more details.
Version 2.5
Dimensions and Physical Signal Assignments
Page 57 of 78
March 26, 2007