Data Sheet
PowerPC 970FX
Preliminary
• In order dispatch of up to five operations
• Specific focus on storage latency management
• Out-of-order and speculative issue of load
operations
into distributed issue queue structure
• Register renaming on GPRs, FPRs, VRFs,
CR Fields, XER (parts), FPSCR, VSCR,
VRSAVE, Link and Count
• Support for up to 8 outstanding L1 cache
line misses
• Hardware initiated instruction prefetching
from L2 cache
• Large number of instructions in flight
(theoretical maximum of 215 instructions)
- Up to 16 instructions in instruction fetch
unit (fetch buffer and overflow buffer)
- Up to 32 instructions in instruction fetch
buffer in instruction decode unit
• Software initiated data stream prefetching
- Support for up to 8 active streams
• Critical word forwarding / critical sector first
• New branch processing / prediction hints
added to branch instructions
- Up to 35 instructions in 3 decode pipe
stages and 4 dispatch buffers
• Power management
- Up to 100 instructions in the inner-core
(after dispatch)
- Up to 32 stores queued in the STQ
(available for forwarding)
• Static power management
- Software initiated doze and nap
• Dynamic power management
- Parts of the design stop their (hardware
initiated) clocks when not in use
• PowerTune
• Fast, selective flush of incorrect speculative
instructions and results
- Software initiated slow down of the
processor; selectable to half of the
nominal operating frequency
General Information
Page 12 of 68
July 15, 2005
IBM [ IBM ]
