PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
Errata Summary
For errata details, see the PowerPC 750-PID 8p Microprocessor Errata List
#
1
Problem
Description
Impact
Solution(s)
Applies to
Version 3.2
L2 cache invalidate may If DPM is enabled during a Possible system failure after Turn DPM off during a
fail with DPM enabled.
Yes
Yes
Yes
global invalidate of the L2 L2 initialization and start-up. L2 tag invalidate.
cache, the global invali-
date may not invalidate all
the L2’s tags.
3
5
8
dcbz that hits in L1
cache may not retry
snoop.
If a dcbz hits in the L1
cache, a snoop received memory may be read by the data that is protected
at the same time to that
address may not be ser- line may become valid in
Stale data from system
Limit use of dcbz to
other bus master, and the
through software syn-
chronization.
viced or get retried.
multiple caches.
Segment register
updates may corrupt
data translation.
mtsr<in> followed by an
Possible access to incorrect Insert isync, sc, or rfi
instruction causing a page real address locations or
data address translation false translation and data
can cause contention for access exceptions.
the segment registers.
between andy mtsr<in>
and instructions that
cause a page data
address translation.
Stfd of uninitialized FPR A stfd will hang the part if Any system using a stfd.
Initialize all FPRs at
POR.
Yes
Yes
(Advisory) can hang part.
its source FPR has pow-
ered up in a certain state.
11
Thermal Assist Unit
Actual TAU errors are dif- If TAU reads higher than
Re-evaluate system
(TAU) accuracy specifi- ferent than those speci-
expected, false temperature thermal design require-
cation error in dd3.2
Datasheet
ficed.
alarms can occur.
ments and calibrate the
TAU.
If TAU reads lower than
expected, it can fail to signal
a temperature alarm.
9/6/2002
Version 2.0
Page44
IBM [ IBM ]
