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IBM25PPC750L-GB500AD2R 参数 Datasheet PDF下载

IBM25PPC750L-GB500AD2R图片预览
型号: IBM25PPC750L-GB500AD2R
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,]
分类和应用: 外围集成电路
文件页数/大小: 54 页 / 1135 K
品牌: IBM [ IBM ]
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PowerPC 740 and PowerPC 750 Microprocessor  
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2  
L2 Bus Input AC Specifications  
Some specifications are shown in the following table as a Function of Maximum Core Frequency (Fmax).  
These specifications refer to the effective Fmax of the part after derating for application conditions. For exam-  
ple, a nominal 450 MHz part running at application conditions that derate its Fmax to 400 MHz will meet or  
exceed the specifications shown for Fmax = 400 MHz.  
L2 Bus Input Interface AC Timing Specifications  
See ”Recommended Operating Conditions,” on page 11, for operating conditions.  
Num  
29,30  
24  
Characteristic  
L2SYNC_IN rise and fall time  
Min  
Max  
1.0  
Unit  
ns  
Notes  
2, 3  
1
Data and parity input setup to L2SYNC_IN, Fmax up  
through 375 MHz.  
1.5  
ns  
24  
24  
24  
25  
Data and parity input setup to L2SYNC_IN, Fmax = 400  
MHz.  
1.4  
1.1  
1.0  
0.5  
ns  
ns  
ns  
ns  
1
1
1
1
Data and parity input setup to L2SYNC_IN, Fmax = 433 and  
450 MHz.  
Data and parity input setup to L2SYNC_IN, Fmax = 466 and  
above.  
L2SYNC_IN to data and parity input hold  
Note:  
1. All input specifications are measured from the Vm of the signal in question to the Vm of the rising edge of the input L2SYNC_IN. Input timings are  
measured at the pins (see Figure 8).  
2. Rise and fall times for the L2SYNC_IN input are measured from 0.5 to 1.5V.  
3. Guaranteed by design and characterization, and not tested.  
Figure 8. L2 Bus Input Timing Diagrams  
29  
30  
L2SYNC_IN  
VM  
24  
25  
VM  
VM  
ALL INPUTS  
Vm = 1.4 V for L2OV = 3.3 V., else Vm = L2OV /2  
DD  
DD  
9/6/2002  
Version 2.0  
Page22  
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