PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
L2 Clock AC Specifications
The following table provides the L2CLK output AC timing specifications for the 750 as defined in Figure 7.
L2CLK Output AC Timing Specifications
See ”Recommended Operating Conditions,” on page 11, for operating conditions.
Num
Characteristic
Min
80
Max
267
Unit
MHz
ns
Notes
1, 5
L2CLK frequency
L2CLK cycle time
L2CLK duty cycle
22
23
3.75
12.5
50
%
2
4
Internal DLL-relock time
L2CLK jitter
640
±
—
±150
0
L2CLK
ps
3, 6
7
L2CLK skew
ps
Note:
1. L2CLK outputs are L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT pins. The internal design supports higher L2CLK frequencies. Consult IBM Pow-
erPC Application Engineering (ppcsupp@us.ibm.com) before operating the L2 SRAMs above core frequency/2. The L2CLK frequency to core fre-
quency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum
operating frequencies. L2CLKOUTA and L2CLKOUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The major component of L2CLK jitter is passed through from SYSCLK. While SYSCLK jitter is less then ±150 ps, L2CLK jitter is also less than ±150 ps.
SYSCLK jitter in excess of ±150 ps causes L2CLK jitter to exceed ±150 ps.
4. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time
duration in nanoseconds. Re-lock timing is guaranteed by design and characterization, and is not tested.
5. The L2CR [L2SL] bit should be set for L2CLK frequencies less than 110MHz.
6. Guaranteed by design and characterization, not tested.
7. Skew between the L2 output clocks is included in the other timing specs.
9/6/2002
Version 2.0
Page20
IBM [ IBM ]
