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IBM25PPC750L-GB500AC2ST 参数 Datasheet PDF下载

IBM25PPC750L-GB500AC2ST图片预览
型号: IBM25PPC750L-GB500AC2ST
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 500MHz, CMOS, CBGA360,]
分类和应用: 外围集成电路
文件页数/大小: 54 页 / 1135 K
品牌: IBM [ IBM ]
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PowerPC 740 and PowerPC 750 Microprocessor  
CMOS 0.20 µm Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2  
AC Electrical Characteristics  
This section provides the AC electrical characteristics for the 750. After fabrication, parts are sorted by maxi-  
mum processor core frequency as shown in the Section “Clock AC Specifications,” on page 14, and tested for  
conformance to the AC specifications for that frequency. Parts are sold by maximum processor core fre-  
quency, subject to the specified application conditions. See ”Ordering Information,” on page 51. Unless other-  
wise noted, all timings apply for all I/O supply voltages.  
Clock AC Specifications  
The following table provides the clock AC timing specifications as defined in Figure 2.  
Clock AC Timing Specifications  
See ”Recommended Operating Conditions,” on page 11, for operating conditions.  
Num  
Characteristic  
Fmax = 300-375MHz  
Fmax 400MHz  
Unit  
Notes  
Min  
Max  
Min  
250  
Max  
Processor frequency  
250  
As specified by  
part number  
As specified by  
part number  
MHz  
6
1
SYSCLK frequency  
25  
10  
100  
40  
31  
10  
100  
32  
MHz  
ns  
1
2, 3  
4
SYSCLK cycle time  
SYSCLK rise and fall time  
1.0  
60  
1.0  
60  
ns  
2, 3  
3
SYSCLK duty cycle measured  
at Vm  
40  
40  
%
SYSCLK jitter, cycle-to-cycle  
Internal PLL relock time  
±150  
±150  
ps  
4, 3  
5
100  
100  
µs  
Note:  
1. Caution: The SYSCLK frequency and the PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, and CPU (core)  
frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section “PLL  
Configuration,” on page 40 for valid PLL_CFG[0:3] settings. Bus operation above 100 MHz is possible, but requires careful timing analysis. Contact  
IBM for details.  
2. Rise and fall times for the SYSCLK input are measured from 0.5 to 1.5V.  
3. Timing is guaranteed by design and characterization, and is not tested.  
4. Short term jitter must be under ±150ps.  
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock  
after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and  
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time  
during the power-on reset sequence.  
6. Under certain conditions, operation at core frequencies below those stated is possible. Contact IBM for details.  
Figure 2. SYSCLK Input Timing Diagram  
1
2
3
4
4
CVIH  
VM  
SYSCLK  
CVIL  
Vm = OV /2  
DD  
9/6/2002  
Version 2.0  
Page14